MCF8316AEVM: Question about SW_BK Voltage waveform

Hi Jenson,

I'll get back to you shortly!

Regards,

Vishnu

Jenson,

Buck regulator is powered by the supply voltage Vm. Control block of the buck regulator controls the duty cycle of the power FETs and regulates the voltage to 3.3V. I think your Buck regulator is configured to 3.3V.  

Regards,

Vishnu.

Hi Vishnu,

For example, in our ordinary buck, the voltage at the SW point will not be biased. For example, 12 to 3.3V buck, then the duty cycle of SW point PWM should be 27.5% (0V~12V) PWM.
I am very surprised why the buck in our MCF has a 3.3V~Vm waveform (as shown in the figure above). Is it my misunderstanding of his topology? Or is it a new control method?

Thanks

Jenson

Hello Jenson,

The team is out of the office due to Thanksgiving holiday here in the US. We will be back in office on Nov 29th, thank you for your patience and understanding.

Best,

Isaac

Hi Isaac,

OK,no problem.

thanks for you reply.

Jenson

Hey Jenson,

Awesome, thanks for understanding!

Best,

Isaac

Jenson,

The output voltage of the buck regulator is compared with the reference voltage (VBK_REF) which is internally generated depending on the buck-output voltage setting. Now, depending on the comparator output going high (VBK < VBK_REF) or low (VBK > VBK_REF), the high-side power FET of the buck turns on and off respectively. When VBK < VBK_REF, high-side power FET turns ON and SW_BK node measures VM which is the peak voltage seen on the SW_BK pin. When VBK > VBK_REF, high-side power FET turns off and SW_BK node measures the voltage across CBK which is same as VBK (circuit now gets simplified to a simple LC circuit).  Hope this answers to your question.

Regards,

Vishnu

Hi Vishnu,

Very clear, thank you for your patience.

This is the basic working principle of buck, so I want to know that if the low-side mosfet is turned on for too long, then the CBK is actually discharging, and the measured Vsw point voltage will decrease. But I didn't see this in my waveform, so can we conclude that we need to use a larger capacitor (such as 22uF of EVM) behind the SW point, otherwise the waveform will be abnormal?

Thanks

Jenson

Vishnu,

Thanks Vishnu!Do we have a minimum limit on the value of this capacitor?

Thanks

Jenson

Hi Vishnu,

Understood,Thanks!

B.R

Jenson