The TI E2E™ design support forums will undergo maintenance from July 11 to July 13. If you need design support during this time, open a new support request with our customer support center.

  • State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 434 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DRV8350: Minimum dead-time

DRV8350S-EVM: Gate signals and phase voltages show great jitter

Ignacio Pedrosa
Prodigy 60 points
Part Number: DRV8350S-EVM
Other Parts Discussed in Thread: DRV8328

Hi,

We have developed a brushless drive based on DRV8350S-RTV (sorry, we are not using the EVM board, but was the only part I could select in the form).

We are evaluating the design and the overall performance yet looks good, but I'm stuck with the fact the gate charge and discharge edges do not happen in a completely deterministic time frame. On the contrary, they "jitter", and so does the phase voltage. The following persistence captures can be of better explanation:

As can be seen, the input PWM signal edges happen predictably and steadily in the time axis, while output gate signals happen along with a range of 50 ns, which seems to increase slightly with temperature. Consequently, the phase voltage shows the same behavior.

In this capture, a 0 set-point was commanded with the current loop disabled to make sure no phase duty other than a perfect 50 % was applied, but the jitter can go even further when phase current is being driven.

I would like to know if this is normal behavior, or if it can be avoided somehow. We are using the Independent PWM mode because we thought the issue was caused by the Vgs protection or the deadtime insertion active with the 6x PWM mode, but the jitter keeps happening. Also, we are trying to reach a 200 kHz PWM frequency, which makes having a low deadtime a desirable capability. We did tests with 50 ns, but small shot-throughs get to happen when the output edge appears the soonest; then, we have to increase the deadtime to give it a safety margin. 

If this cannot be avoided, is there a maximum tolerance to be expected? At least this would help us choose the smallest deadtime that is safe to use.

Finally, can this jitter cause any known control issue? The output current looks smooth, but I wonder if this can introduce a "deadband" effect in the smallest currents around 0 A.

Thanks in advance for your help. Any further data you require, please let me know.

  • 0
    TI__Mastermind 26046 points

    Hello Ignacio, 

    It is known that jitter can across all our devices with Smart Gate Drive, due to inputs operating as a level shifter and as a control switch for our pre-drivers to control the GHx/GLx outputs along with many handshakes and internal timings. 

    One thing you can try is to utilize Independent Mode and see if the jitter variation decreases, using deadband from the MCU rather than Smart Gate Drive to have more control over gate drive outputs going high. 

    We need time to inquire about jitter variability and tolerance, we can get you a reply after the holiday about this. 

    Thanks,
    Aaron


  • 0 in reply to Aaron Barrera
    Prodigy 60 points

    Hello Aaron,

    We are already using the independent mode, including the capture shown.

    We'll wait for further performance data on this after the holiday season.

    Merry Christmas!

  • 0 in reply to Ignacio Pedrosa
    TI__Mastermind 26046 points

    Good to know, I've reached out to design in regards to jitter time across Smart Gate Drive devices. 

    Merry Christmas to you too!

  • +1 in reply to Aaron Barrera
    TI__Mastermind 26046 points

    Hi Ignacio, 

    Jitter in Smart Gate Drive devices is due to synchronization of the input to the internal oscillator to pass the inputs to the predrivers. The internal oscillator frequency is which is 20 MHz (50ns period). Therefore, the gate driver jitter can occur from 0-50ns from input to output. 

    On the contrary, DRV8328 (just recently RTM'ed) is not synchronized with the internal oscillator since it is not a Smart Gate Drive device, so there is no jitter from inputs to gate driver outputs. 

    Thanks,
    Aaron

  • 0 in reply to Aaron Barrera
    Prodigy 60 points

    Hi Aaron,

    Thanks, this explains a lot.

    I would recommend including this information in the datasheet, if you would accept the feedback.

    Regarding the DRV8328, that would be a very interesting option if it was not for the 60 V rating (we need the 100 V rating, or a least an absolute minimum of 80 V). 

    In any case, now that I see there is not much to do to avoid the jitter effect, I will focus on analyzing any possible uncontrolled/uncommanded current to a low inductance load. 

    Thanks!