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DRV8705S-Q1EVM: Drive issue

Part Number: DRV8705S-Q1EVM

Hi team

Here's some issues from the customer may need your help:

1. Using the MCU's port, simulate the spi and see through the oscilloscope that the analogue spi transmit configuration drv8705 data was successful. The parameters are as follows:

A. Configuring the IC_CTRL Register: 0x0436

B. Configuring the BRG_CTRL Register: 0x0540

C. Configuring DRV_CTRL_1 Register: 0x0677

D. Configuring DRV_CTRL_2 Register: 0x0777

E. Configure DRV_CTRL_3 Register: 0x0804

2. The IN1/EN configured for the drv8705 is the PWM input, the IN2/PH is the I/O input, and the positive reversal of the motor is controlled by the high and low levels.

3.Configure the DRVOFF and SLEEP pins of the drv8705 high.

Note: using PH/EN H-Bridge Control (BRG_MODE = 01b or MODE = Level 2)

Issue: After configurating as above, IN1? En and IN2/PH, output good, but GH1, GH2 output high, GL1, The GL2 outputs are low, SH1 is high, and SH2 is high.

Could you help check this case? Thanks.

Best Regards,


  • Hi Cherry.

    >>A. Configuring the IC_CTRL Register: 0x0436

    Which means EN_DRV(D7) = 0, therefore "Driver inputs are ignored and passive pulldown is enabled". In other way to say, OUTPUT is disabled.

    Please ask customer to try to set EN_DRV=1. One note. We recommend to set EN-DRV=1 (and CLR_FLT D0=1 as well) after completion of other registers(e.g address 05,06,07..) are programmed.

    If output does not work after above trial, I recommend to read back STATUS registers(0x00,0x01,0x02. Then we can see what type of fault is happens.


    Shinya Morita

  • Hello Shinya Morita,

    Thanks for your help here! 

    Here's some additional info may helpful:

    When using drv8705s-q1, the related register configuration is shown as Figure 1 below. When configured as Figure 1, the output should be Active Free-Wheeling: Low -FET, but the output is still Active Free-Wheeling:High-FET, as shown in Figure 2.

    The configuration parameters are checked through the oscilloscope and the waveform of the configuration parameters is normal.

    Figure 1:

    Figure 2:

    They have made some changes, and the reading values is as follows:

    The value of IC_STAT_1 Register is:0x80 ,the value of VGS_VDS_STAT Register is:0x00, the value of IC_STAT_2 Register is:0x80.

    (The Chinese in the figure above is "address")

    Thanks and regards,


  • Cherry, 

    it is a US holiday today.  Will respond by tomorrow. 



  • Hi Cherry,

    IC_STAT read result provides hits to debug. IC_STAT_2 =80 means PVDD had UVLO fault. It means PVDD should have dropped then fault happened. Customer can check PVDD stability.

    nFault pin should go low when PVDD_UV happens-FYI.


    Shinya Morita

  • Hi Ryan, thanks for your remind!

    Hi Shinya Morita,

    If they do not have Standby State when configuring the spi parameters, can the registers of drv8705s-q1 be configured successfully directly in Operating State?

    As can be seen from the schematic, both PVDD and DVDD are directly connected to the power supply and should not have Standby State. The schematic is as follows:

    Thanks and regards,


  • Hi Cherry,

    The registers of drv8705s-q1 can be configured successfully directly in Operating State.

    >>As can be seen from the schematic, both PVDD and DVDD are directly connected to the power supply and should not have Standby State. The schematic is as follows.

    This is pretty normal way same as EVM. No problem at all.


    Shinya Morita