• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 171 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8313: Datasheet Clarification

Mark Philip Felipe
Genius 9705 points
Part Number: DRV8313
Other Parts Discussed in Thread: DRV8311, DRV8316

Hi Team, seeking so details that may need your assistance.

The datasheet states that the UVLO Vm RISING is 6.3Vtyp to 8Vmax. I was hoping to get some more information on the UVLO functionality. Do you have any information on the threshold for Vm falling? Is there a hysteresis circuit implemented?

What does the startup timing of this chip look like? Basically what is the timing of the UVLO Vm rising threshold to the time that the H-bridge actually starts responding to the PWM control inputs?

What would the repercussions be of a ~8A current spike through the H-bridge? Is there any concern of latent damage?

Assuming that the duty cycle of the current spikes was low enough to not be a thermal concern, is there any other concern to the FETs? What about the internal OCP sense circuitry? I assume there are internally implemented sense resistors.

And how high of a current spike through the H-bridges the designers would feel comfortable would not cause damage.

Thank you.

-Mark

  • 0
    TI__Mastermind 26046 points

    Hi Mark,

    Typically our DRV devices implement a hysteresis for UVLO rising and falling, however I do not see a hysteresis for UVLO in this device. We could test this on a DRV8313EVM to test the hysteresis. 

    The startup timing should be listed as twake, the amount of time it take for logic to be enabled after UVLO rising is exceeded. Unfortunately the electrical specifications do not show much information, so my assumption would be 1ms before ENx/INx inputs correspond to an output on the OUTx pin.  

    Overcurrent is sensed I believe through a sense FET on the LS FET, and is configured for 5-A overcurrent limit after a deglitch of tOCP. A better method would be to use a trip shunt resistor that connects PGND1 - PGND3, and ties the shunt to a common ground where overcurrent is measured from the voltage across the shunt. 

    A current spike depends on the amount of inductance at the VM, OUTx pins, and GND of the PCB. If there is a lot of inductance, voltage and current spikes could exceed transients or cause coupling into the low-side FET's gate via dV/dt coupling. In the case of a shoot through, the OCP limit should protect the device and FETs from damage. Staying within the recommended specifications of the device and good PCB layout should reduce risk of causing damage. 

    I also recommend the DRV8311 if the voltage application is <12V, or DRV8316 if the voltage application is <24V. These are new integrated MOSFET drivers with smaller packages, higher temperature ratings, and larger peak currents. DRV8311 is released for production samples, and DRV8316 will release in next few weeks for production. 

    Thanks,
    Aaron