Other Parts Discussed in Thread: DRV8311, DRV8316
Hi Team, seeking so details that may need your assistance.
The datasheet states that the UVLO Vm RISING is 6.3Vtyp to 8Vmax. I was hoping to get some more information on the UVLO functionality. Do you have any information on the threshold for Vm falling? Is there a hysteresis circuit implemented?
What does the startup timing of this chip look like? Basically what is the timing of the UVLO Vm rising threshold to the time that the H-bridge actually starts responding to the PWM control inputs?
What would the repercussions be of a ~8A current spike through the H-bridge? Is there any concern of latent damage?
Assuming that the duty cycle of the current spikes was low enough to not be a thermal concern, is there any other concern to the FETs? What about the internal OCP sense circuitry? I assume there are internally implemented sense resistors.
And how high of a current spike through the H-bridges the designers would feel comfortable would not cause damage.
Thank you.
-Mark