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DRV8701: OCP early trigger case

Part Number: DRV8701

Hi Team,

Customer uses our EVM for testing 2 cases, each condition is like below.

For case2 customer wants to know if any possible reason it seems early triggering OCP, thx!

case1: 

VREF = 1.617v

Rshunt = 3.5

PWM 20kHz

duty: 62% reaching OCP

SO = 1.5v

=> calculation match

case2: 

VREF = 1.617v

Rshunt = 3.5

PWM 40kHz

duty: 42% reaching OCP

SO = 0.98v

=> calculation not match

Andrew

  • Hi Andrew,

    My guess is that the FETs are not getting fully enhanced due to the very short ON pulse when the frequency is 40kHz. When the FET is not fully enhanced, the RDSon will be greater than when fully enhanced.  Since the DRV8701 measures the VDS (drain-to-source) voltage and compares it to the VDS OCP limit. Due to the higher RDSon resistance when FET is not fully enhanced, the VDS voltage can be higher than VDS OCP limit (~1V typ).

    To attempt to fix this problem, you can try increasing the IDRIVE_source to the 150mA to help the MOSFET enhance quicker.