Hi, Team
In my application, during the startup timing, the Gate Drive Pin (GLX) keep a high level voltage(about 12V) until VDDIO voltage become normal.
How can you explain this issue? And any other suggest give me to eliminate this abnormal GD voltage?
Thanks very much!
CH1:P5_EXT(VDDIO)
CH2:24V_BUS_V(DHCP)
CH3:GD_X_BOT(GLX)
CH4: ignore
Adam,
nASCIN and ASCSEL pulled up by 4.7k resistor.So, I think this two signal are Low.
P12V(PVDD) is powed up behind the P5_EXT .
Regards,
-Ming
Ming,
nASCIN input is low until VDDIO comes up since VDDIO powers VINT:
When nASCIN is low, the device is in low side ASC so the low side gate will turn on.
Once VDDIO is high enough to clear the VIH of nASCIN then ASC will be disabled and the LS gate turns off.
Regards,
-Adam
