DRV8343-Q1: VM Blackout Behavior

Shinichi Yokota

Part Number: DRV8343-Q1

Hello,

When V_VM drops below its Min operating range 5.5 V in a system shutdown sequence, for example, and then it rises again on the way (3.3 V, for example) before reaching 0 V, will the DRV8343S-Q1 always successfully restart? Or, can it fail? How will the DRV8343S-Q1 behave?

In this case, 5.5 V is always applied to the ENABLE pin regardless of the V_VM voltage.

Best regards,
Shinichi Yokota

over 3 years ago

+1 Dung Dang over 3 years ago

TI__Genius 17802 points

HI Yokota-san,

this behavior is captured by our undervoltage circuit/protection feature specifically on our VUVLO spec in our datasheet here: https://www.ti.com/document-viewer/DRV8343-Q1/datasheet/electrical-characteristics-x8427#x8427

Specifically, the system shutdown sequence happens when VM drops below VM falling VUVLO spec, and restart begins when VM increases above the VM rising VUVLO spec highlighted in the table below. Note that there is a 200mV (typ) hysteresis, as well as deglitch time associated with this protection circuit.

With that in mind, in the the scenario you described, if VM drops below VM falling VUVLO spec (3.3V is sufficiently below), and then recovers above VM rising VUVLO spec max (5.9V for this device), and this transition takes longer than deglitch time spec, device is expected to restart.

Hope that helps!

~Dung

0 Shinichi Yokota over 3 years ago in reply to Dung Dang

TI__Genius 9715 points

Dung-san,

I'd like to ask one more question.

I'm concerned if the DRV8343-Q1 always successfully shuts down as the V_VM goes down and it always successfully restarts again as the V_VM goes up when the DVDD regulator output is applied to the ENABLE pin to keep the ENABLE pin High.

Is it OK to tie the DVDD pin to the ENABLE pin to keep the ENABLE pin High in real applications?

Best regards,
Shinichi Yokota

0 Aaron Barrera over 3 years ago in reply to Shinichi Yokota

TI__Mastermind 26046 points

Hi Shinichi-san,

Dung will answer your question tomorrow.

Thanks,
Aaron

+1 Dung Dang over 3 years ago in reply to Shinichi Yokota

TI__Genius 17802 points

Hi Yokota-san,

if the customer does not need to ever put the device into sleep mode, it is OK to tie ENABLE pin high. They can certainly do that by leveraging the DVDD regulator output (3.3V is considered high logic). However, to limit current draw to this pin, you can add a pull-up resistor to the design.

~Dung

0 Shinichi Yokota over 3 years ago in reply to Dung Dang

TI__Genius 9715 points

Dung-san,

I'd like to ask one additional question. What kind of situation does this description assume? If it's a sink current into the ENABLE pin by its internal pull-down resistor of about 60 kΩ, I don't think it would have an impact on the DRV8343S-Q1 operation since it's only about 55 µA (≈ 3.3 V / 60 kΩ). Besides, which voltage do you assume the pull-up resistor is tied up to?

Dung Dang said:
However, to limit current draw to this pin, you can add a pull-up resistor to the design.

Best regards,
Shinichi Yokota

+1 Dung Dang over 3 years ago in reply to Shinichi Yokota

TI__Genius 17802 points

Hi Yokota-san,

you are correct, ENABLE pin does have an internal pull-down and should effectively limit current draw per your calculation. In this case additional pull-up is not necessary. That guidance is typically mentioned as best practice when connecting pins directly to supply when you might not know how the pins are internally configured.

~Dung

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DRV8343-Q1: VM Blackout Behavior