Other Parts Discussed in Thread: DRV8872,
Hi folks,
I have an in-house designed and built control board used to control some of our test equipment, it has 2 relays configured as a H bridge. These relays have been wearing out and failing (50k+ ops) so I wanted to design a direct replacement using a solid state H bridge. So I designed a replacement and built one test sample using a DRV8872. It tested out ok but tripped as soon as I tried to use it for the end use case . . . it seems the current inrush due to the input capacitor of the device I was connecting it too was too great.
So back to the drawing board, this time with a DRV8842 which can control the output current, "maximum current through the load is regulated by a fixed-frequency PWM current regulation,", I've designed my circuit and laid out the PCB.
I've noticed a few anomalies in the data sheets, the version I have is a March 2016 revision, I think that is the latest.
- Section 5. Pin Configuration and Functions: CP1 CP2 says "Connect a 0.01-μF 50-V capacitor between CP1 and CP2." Section 10.1 Layout guidelines says "A low-ESR ceramic capacitor must be placed in between the CP1 and CP2 pins. TI recommends a value of 0.1 μF rated for VM ." the diagram also shows 0.1uF
- Section 8.2 Typical Application shows a 0.1uf cap between VM and VCP V3P3OUT is grounded via a 0.47uF cap. Section 10.1 Layout guidelines says "A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. TI recommends a value of 0.47 μF rated for 16 V." and "Bypass V3P3OUT to ground with a ceramic capacitor rated 6.3 V." this is shown on the diagram as 0.1uF
- Section 8.2.2.1 The example calculation for the resistor divider to set the VREF is incomplete "Set R2 = 10 kΩ and set R1 = kΩ" R1 does not have a value.
I know these anomalies are not very severe and easily worked around, I thought I would mention them so they might get fixed in a future revision.
