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DRV3255-Q1: DRV3255 power up design questions

Part Number: DRV3255-Q1

Dear Teams

We are working on project with DRV3255, there are some questions as below

1.  our circuit as below, in our design we don't need sleep function. so we connect nSleep pin to 5V

but in some case (ex: reboot), if 5V is build up faster than 48V, UV error (IC_STAT_3 = 0x55) shows up and can't be reset by IC_CTRL_1 bit0  even after all power is normal 

2.  On our board test, when power up before SPI ENABLE_DRV=1b1, high side vgs will have abnormal output

this waveform we use 2n7002 signal level mosfet as gate drive test load, no motor or other load connected for inverter, and use differential probe for high side Vgs

 we also found the abnormal high side Vgs will cause VGS_HA_L or VGS_HB_L or VGS_HC_L error (random)

We also double check with TI's EVB, after nSleep become high, there is some ripple at high side Vgs but not large enough to trigger error

before enable drive we need to assure all gate driver output is high z or low

is there any setting error or linkage current at high side gate need to be take care?

best regards,


  • Albert,

    1. Can you add a buffer or use a GPIO to control nSLEEP? 5V will build faster than 48V easily and we prefer to not have voltage on the nSLEEP pin before the device is powered up. Can you show us the power up timing of nSLEEP with PVDDS, and DCHP in the same plot?

    2. I had provided some questions on item (2) over email. Most of those questions are answered above, thank you. Remaining question is if the BST is charging at this time, maybe this is causing the abnormal waveform. Can you measure the BST caps to see if they are the cause of this abnormal voltage?