DRV8343H-Q1EVM: How to handle vdrain when using as 3x HS and 3x LS independent drives

Part Number: DRV8343H-Q1EVM

I am looking to use this as a driver for 3x HS and 3x LS independent drivers to drive a total of 6 independent solenoids. The HS drives will be connected to power internally so vdrain makes sense to connected. However, for the Low sides power may be sourced externally meaning vdrive and VM may be zero while the LS drain (the dlx pins) may be non zero (may even be 36v).

Is there a reference design on how to maintain the voltage requirements of the gate drivers, vdrain and Vm pins in this? I have seen putting a diode from the dlx pins to the vdrain pin, but if the external source power is higher than VM that may cause issues with the over current protection for the high side gets or the requirements between Vm and vdrain. 

Any help is appreciated. 

  • Hi Ben, 

    Thanks for reaching out via our e2e motor drivers forum. 

    I will take a look at this and aim to give a response by early next week, middle of next week at latest. 

    Best Regards, 
    Andrew 

  • Hi Ben, 

    Thanks for your patience on this matter - please see response below: 

    1. Can you take a look at Section "8.3.1.1.8 Independent MOSFET Drive Mode" of the datasheet and let us know if this works for you?  
      1. specifically, looking at the diagrams and details on page24?
      2. this is a direct implementation of handling 6 independent outputs
    2. Would it be possible to provide a diagram/drawing to clarify what you are requesting? 
      1. I suggest for us to use the 'Functional Block Diagram' from section 8.2 on page18 as your baseline drawing, and mark-up as needed
      2. the main part that I am unclear on is "However, for the Low sides power may be sourced externally meaning vdrive and VM may be zero while the LS drain (the dlx pins) may be non zero (may even be 36v)"
        1. is there a particular application requirement why VM pin can't just be tied to the same voltage as the VDRAIN pin and MOSFET power stage VDRAIN? Our device typically expects VM to be powered in order for the DRV device to function 
    3. Here are the main things to look out for, regarding the scenarios you described:
      1. VM_UVLO (ref section 8.3.5.1 in datasheet) 
        1. this should ideally be above 5.9V to avoid triggering a device fault and putting the device in partial shutdown 
      2. VDS monitors for VDS_OCP feature need to be across the drain-source terminals of an external MOSFET. 
        1. when the MOSFET channel is turned ON, the VDS will expect to see a very small voltage differential - otherwise you will get a fault. 

    Page24 diagram of independent mode with two high-side loads. 

    VM and VDRAIN connection

    Best Regards, 
    Andrew 

  • Referencing the figure, My controller has a battery disconnect turned on by ignition Pin so the battery can be on, while the controller internal power is off. if the low side switch Load is connected to external power (standard for a low side drive in some applications), then VM/Vdrain would be 0V while the DLx pin is high (maybe 36v), however the datasheet states the DLx pins can only be 5v above vdrain. is there a way to protect against this case? also there are requirements for any pin to be able to handle 36v or gnd while the battery is connected or disconnected which causes the same issue (without a battery disconnect circuit)

  • Hi Ben,

    My apologies for the delay in getting back to you. We will look into this in more detail and try to provide a response early next week.

    Regards,

    Anthony Lodi

  • Hi Ben, 

    Thanks for your patience - updated response below.

    From looking at the diagram, it appears that the abrupt cutoff of VDRAIN pin from MOSFET power stage VDRAIN would likely cause issues if SHx is still connected to the DRV IC. This is a commonly reported limitation, and I'll follow up with our systems team tomorrow to see if I can provide a workaround or at least highlight the failure mechanism for a better description of internal circuit-level behavior.

    I would like to ask if it'd be possible for your system to implement cutoff switches for the connection between MOSFET power stage switch node and the DRV IC's SHx pin? This app note goes into further detail about supplying external MOSFET gates using the DRV IC's VCP pin: https://www.ti.com/lit/an/slla397/slla397.pdf

     

    These resources below may also help in the system-level implementation of techniques like STO:  

    Best Regards, 
    Andrew 

  • Hello, 

    Any update from your systems team on the Vdrain / SHx divergence options?

    For the second "cuttoff" option, this would limit the option for overcurrent protection would it not? as now the SX pin isnt reading the actual value?

    Thanks,

    Ben

  • Hi Ben, 

    Yes, I will aim to provide an updated response today - apologies for the delay 

    Best Regards, 
    Andrew 

  • we potentially have an idea for a circuit as well, would you have time for a call?

  • Hello Andrew,

    we are still working on the solution for the 6 independent drives, but if we just look at the 3 drives in series, perhaps the diodes below save us? there is a diode in the mosfet SHx to Vdrain and the and the flyback diode from DLx to SHx. does this save us from the SHx/DLx to Vdrain requirements or am i missing something?

  • Hi Ben, 

    Thanks for your patience - and updated response is below
    (My apologies for the delays, as I am currently dealing with Covid symptoms and this has been a particularly hectic week) 

    Please let me know if this resolves your question, and help mark the thread if so.

    So let's first consider our main abs max ratings that apply in this system-level evaluation: 

    • DRV IC pins to be aware of are SHx, Vdrain, VM, and VCP/CPH 

    Next, let's identify scenarios that we want to avoid, and why: 

    1. VM must be powered on at all times where Vbattery is connected to the load and has a path to the device's SHx pin 
      1. this is because if VM is unpowered, then charge pump VCP=0V (references to VM)
      2. the resulting consequence is that SHx voltage (e.g. 24V) will have high Voltage diff w.r.t VCP and will flow through HS pre-driver internal FETs, and then also damage a diode that exists between VM and VCP. 
      3. this is why there's a spec max between SHx and VM, and a spec max between VCP and VM 


    2. Ideally during device operation (driver switching GHx/GLx=H/L to drive the ext FETs), we want VM and VDRAIN to be roughly the same voltage 
      1. this is because VM is used to generate VCP voltage to power the HS pre-driver.
        1. Once again, this VCP references VM and usually the relationship is VCP= VM+11V
      2. the HS predriver, however, generates VGS voltage by pulling GHx up to VCP so that it is ~12V higher than SHx  
        1. and SHx is usually expected to be between 0V and VBAT (a.k.a MOSFET Vdrain, not Vdrain pin) 
      3. Therefore, if your VM is much higher than your MOSFET Vdrain or vice versa, then the HS gate-source differential could be too high and cause damage to the internal HS clamping diode or external HS MOSFET of a half-bridge
      4. your system may still be safe as long as you don't try to toggle INHx=H under these circumstances, so that HS pre-driver doesn't 
    3. So what exactly is the function of the VDRAIN pin of the IC? 
      1. VDRAIN pin is a sense input to HS VDS comparator, and it also powers the HS VDS comparator. 
      2. therefore, if your VDRAIN pin is disconnected, then you could experience issues such as unreliable HS VDS monitor behavior
      3. also, you wouldn't want to have SHx=24V while VDRAIN pin is tied directly to ground, since I'm not sure if it's intended to experience that voltage and polarity. However, as your VDRAIN pin is floating (not tied to GND), I think we may be okay here. 
      4. so the voltage applied to this pin is less about biasing the device in a way that causes risk of overstress, but more-so about voltage bias needed to ensure HS VDS monitor proper functionality 

    In conclusion, you might not need a clamping diode after all. 

    • I think if your system keeps VM pin powered on to same level as your VBATTERY (MOSFET power stage VDRAIN)] voltage, then the system should be okay. 
    • disconnecting VDRAIN pin is not ideal due to impact to HS VDS monitor, but it may be okay if you just leave it floating. 
    • maybe you can leave a diode between the MOSFET VDRAIN and the DRV IC's VM pin? That way, you ensure that the DRV IC's VM pin is properly powered so long as the Battery is connected to the load 

    Best Regards, 
    Andrew 

  • Thank you for the thoughtful reply and hope you are past the worse of your COVID. 

    The main scenario I'm worried about is troubleshooting where there is no power to the vdrain or vm, but a tech puts power to the SHx or dLx pin. 

    In this case the inh wouldn't be activated since we aren't powered. Also, when this is happening we won't worry about over current protection as it isn't powered. So this is good. 

    The VM pin and vdrain would be "disconnected" (it has a diode to reverse flow as well) from battery due to a STO power disconnect we have upstream this device which means it would b

    As such I believe the only concern we have left is blowing the diode between SHx / DLx and VM. As stated before how do we limit reverse current. If VM goes high, it will power anything on that rail which potentially would blow the diode. Am I thinking about this correct?

    I would be happy to have a call to walk you through our schematics. 

    Ben

  • Hi Ben, 

    Thanks for the kind comments and additional info 

    For clarification on the VM pin case, 

    • VM being unpowered while SHx is powered is likely to cause issues
    • VM being powered while SHx is powered is ok, even if VDRAIN pin is not connected 

    Let me double check one more scenario with my team members to see how customers w/ STO implementation have done this historically - will aim to provide a response within next 2 days, and can suggest a WebEx call as needed near the end of the week 

    Best Regards,
    Andrew 

  • Hi Ben, 

    Closing the e2e thread for now - will continue to align over email 

    Best Regards, 
    Andrew