DRV8300: board review

Part Number: DRV8300
Other Parts Discussed in Thread: INA240

Hello Ti,

i’m developing a new motor control board and wanted to ask if you could please take a look at it.

Board specs (10cmx10cm) (Top: red, Layer 2: yellow, Layer 3: green, Bottom: blue):
4 Layer, 2oz other layer, 0.5oz inner layer

Stackup power section: top=gnd, bottom=vdd, layer 2=gate traces, layer 3=current sense traces
Stackup control section: top=pwr/signal, layer 2=gnd, layer 3= pwr/signal, bottom=gnd

Rated voltage: 50V (all caps on vdd will be rated to 100v)
Rated current: 60A (not sure if I get thermal problems with the pcb, I will see)

Switching frequency: 10kHz-40kHz
All ceramic caps will be double the rated voltage what is needed.

Gate driver: DRV8300 with external diodes (the gate traces are 70miles wide because of 0.5oz in inner layer). I will start with 30 ohm gate resistors and later I try to tune it (slla385a.pdf). the bootstrap caps will be around 200nf-300nf (calculated from the datasheet equations), is this ok? There are one 100nF and 2.2uF on the supply pin(12V) and an elko with 100uF a bit away.

Mosfets: IRFB4110PBF, 130A, 100V, 4mOhm Rdson, 150nC qg, 43nC qgd, 50ns trr bodydiode.

Caps: 9x330uF vdd-gnd, 3x2.2uF (double stacked) vdrain-gnd and 3x1uF vdrain-source(LS-FET)

All ceramic caps will be double the rated voltage what is needed.

Snubber: 2x between ground and vdd on all three phases (if I need them)

For current sensing, the ina240 are used with 1mohm shunt resistors. What do you think about the cut-out of the analog section, is this ok or should I use a pure ground plane?

What I’m really unsure about is the ground connection from power section to the control section. Normally I would put it on the left side (picture below where de vias are) but I’m a little bit concerned about the gate return currents from the low side fets. Therefore, I made 4 ground connections near the gate traces (picture below). I’m not sure if this is a good idea, what would you do?

Here are the layout and schematic (the microcontroller board is plugged onto the two headers on the left and right):

GND Planes:


VDD Plane:


All Planes:


Without Planes:


3D:


Power Stage (Phase A, B and C similar):


Gate Drive:


Current Sensing:


Supply:


Hall/QEB Sensors:


Voltage regulators:

  • Hi Daniel,

    Thanks for sharing the board, we will need some time to gather the info and review. We will give feedback next week. 

    Thanks,
    Aaron

  • Hi Daniel,

    We should have feedback in the next couple business days.

    Thanks,
    Aaron

  • Hi Daniel,

    Sorry for the delay. As a general reference, looking at the provided EVM files associated with the DRV8300 is always a good start for schematic and layout considerations: https://www.ti.com/lit/zip/slvc817

    Here is my feedback:

    Schematic

    Gate Drive

    • RC filters not required on PWM inputs
    • DRV8300DI integrates bootstrap diodes, so D9 D10 and D12 are not needed. If DRV8300NI is used, then these bootstrap diodes are required
    • If 100nF bootstrap caps are used, and GVDD is a steady voltage source, then only minimum 10*CBSTx = 1uF capacitance (or more) rated for 25-V is okay…100uF is overkill and will be a very large capacitor.
    • Ensure bootstrap caps are rated for 2x motor voltage

    Power Stage

    • If stronger sink current is required, recommend adding sink resistor and diode in parallel with the gate resistor. Otherwise source and sink current will be similar

    Current Sensing

    • Ensure IN- is connected to GND at the low-side of the shunt resistor R3, do not directly connect to GND

    I omitted feedback on the HALL/QEB sensors and voltage regulators as I am not an expert on how those products work, but I am content with the 12V/5V/3.3V/CSA voltage reference rails.

    Layout

    The layout is actually very nice and impressive, especially the DRV8300, gate drive paths, powerstage, and components placed near the power stage. The rails have good copper pours and the gate drive traces are wide enough to minimize inductance, so this powerstage does a good job of mitigating as many parasitics as possible. 

    My only concern is the IRFB4110PBF FETs you are using. Any time you use a TO-220 package MOSFET, the long leads add significant inductance and can affect gate drive performance when sourcing and sinking higher gate currents, so just be on the lookout when monitoring the gate drive output waveforms when testing this. Since there is a gate-to-source diode on each gate drive output, the gates should not overshoot which is good. And since the gate drive traces are wide and external components (snubbers, Rgs resistors) are placed close to the FETs, you are mitigating as much parasitics as possible which will improve the performance of switching the FETs. 

    For current sensing, the ina240 are used with 1mohm shunt resistors. What do you think about the cut-out of the analog section, is this ok or should I use a pure ground plane?

    What I’m really unsure about is the ground connection from power section to the control section. Normally I would put it on the left side (picture below where de vias are) but I’m a little bit concerned about the gate return currents from the low side fets. Therefore, I made 4 ground connections near the gate traces (picture below). I’m not sure if this is a good idea, what would you do?

    As suggested before, the best performance of the INA240 is using a Kelvin-connection, in which you route a differential pair of traces from the top and low sides of the shunt to the inputs of the CSA, and place the filtering components as close as possible to the CSA. Below is a simplified example. 

    For the ground connection between the power section to the control section, we recommend splitting the ground planes, but connecting them together using a low-impedance connection such as a 0-ohm resistor or a net tie. See below for an example. 

    Hope this helps!

    Thanks,
    Aaron

  • Thank you a lot for your feedback Aaron, it really helped. I think there was no delay, you responded quite fast.

    Schematic:

    Gate Drive:
    I removed the input filter. What would be an example use-case? Noise environment near the PWM input traces?

    Power Stage:
    Ok, I thought the DRV8300 has different sink and source currents (max 1.5A sink, 0.75A source).
    Maybe I am misunderstanding this, but does it only have different source and sink currents if I add the extra components (diode and resistor)?

    I added the diode and resistor for higher sink current, you can see it in the picture below. Because this needed a little bit more space, I increased the ground polygon under the shunt resistor (orange circle in picture) to ensure a good ground connection for the vdrain-gnd capacitor (purple rectangle in picture). Do you think I will have any problems with the kelvin connection in this case (orange circle picture)?


    Would this be better? (TOP/Red=GND, BOT/Blue=VDD)


    Layout:
    Thank you that is nice to hear, I took me a long time and several boards to get it this way.
    I know about the higher inductances of the TO220 but as it is it is very cheap to produce and easy to make a housing for this pcb. It’s more for development purposes, later I will try something like this:




    I have a last question about the ground connection. As you suggested I added a 0ohm resistor to connect the grounds. I’m not sure where to place them, therefore I added 4 resistors, 3 are placeholders, I only use one. I will conduct some tests and try to find out what the best place would be, but do you have a recommendation? I marked the resistors with blue circles in the picture below.

    I don’t know why but I would use one of the two on the left. I think the second(R69) resistor would be the better one. If I use the left resistor, the high frequency return currents (rising/falling edges from pwm signal) of the gates from the low side fets has to travel a longer distance along the gap. Could this have negative effects on the switching performance, like more oscillations on the gate signal? I’m asking because I used gate drivers with SLX pins in the past.

    A completely different idea would be, to put the DRV8300 on the power ground like in the picture below and connect them anywhere in the green rectangle. What do you think of this?


    Best regards,
    Daniel

  • Hi Daniel, 

    Our team is currently out of office today for July 4th holiday in the US - but we will review your question and aim to provide a response by end of the week. Thanks!

    Best Regards, 
    Andrew 

  • HI Daniel,

    Gate Drive:
    I removed the input filter. What would be an example use-case? Noise environment near the PWM input traces?

    It's okay to use if there is any high frequency noise. But DRV8300 has an input deglitcher delay used to filter any noise/transients <20-40ns, and an internal pulldown of 100kohm, so there's not really a need for input filters on the input signals. 

    Power Stage:
    Ok, I thought the DRV8300 has different sink and source currents (max 1.5A sink, 0.75A source).
    Maybe I am misunderstanding this, but does it only have different source and sink currents if I add the extra components (diode and resistor)?

    Yes, DRV8300 has 0.75A peak source and 1.5A peak sink current, if there is no resistors used or the resistance values are very small (1's of ohms). But the more gate resistance added, the less your peak source/sink gate current will be because the gate resistor will limit each gate current. For instance, if you use a 10 ohm gate resistor, then ISOURCE = GVDD/(R_gate + R_PU), and ISINK = GVDD/(R_gate + R_PD), where R_PU = internal pullup Rdson of the pre-driver and R_PD = internal pulldown Rdson of the pre-driver. Therefore, Rgate dominates (and limits) the gate currents. 

    Using a source resistor + sink resistor with diode topology allows for adjustable source and sink currents.

    Do you think I will have any problems with the kelvin connection in this case (orange circle picture)?

    Kelvin connection looks fine still, this can go through different layers. 

    Would this be better? (TOP/Red=GND, BOT/Blue=VDD)

    Yes, looks good.

    Thank you that is nice to hear, I took me a long time and several boards to get it this way.
    I know about the higher inductances of the TO220 but as it is it is very cheap to produce and easy to make a housing for this pcb. It’s more for development purposes, later I will try something like this:

    Good to know. I am not concerned as much about TO220 package because of the well-designed gate driver and powerstage layout. 

    I have a last question about the ground connection. As you suggested I added a 0ohm resistor to connect the grounds. I’m not sure where to place them, therefore I added 4 resistors, 3 are placeholders, I only use one. I will conduct some tests and try to find out what the best place would be, but do you have a recommendation? I marked the resistors with blue circles in the picture below.

    Not sure how much the physical placement of the 0-ohm resistor affects the split-ground topology, but the goal is to connect the GNDs together without motor current coupling noise into the digital signals. So the 0-ohm resistor connects the grounds together at only one point so that there is no voltage potential difference between the grounds without adding inductance. 

    Start off with one resistor and see how performance is; if you see motor noise coupling into the digital grounds then adding more resistors will be a good idea. 

    Could this have negative effects on the switching performance, like more oscillations on the gate signal? I’m asking because I used gate drivers with SLX pins in the past.

    Longer current paths can result in more inductance if the path is thin, narrow, and cannot support the current return path back to the driver. Ensure the grounds have stitching vias between all layers and that the ground return paths are not narrow. Since you have dedicated ground planes on many layers of the board, I suspect that this won't be an issue as long as these grounds are connected well (i.e. stitching vias) verus a single ground via, like a power supply connector. 

    The more ground you can allocate for power ground and the DRV8300 ground, the lower the inductance will be. A good strategy is to place the power ground pour on that side of the board, repeat that pour across multiple layers, and use stitching vias to connect the grounds together with the stitching vias. Then connect the power ground to the logic ground either at the top or bottom using the 0-ohm resistors. 

    Thanks,
    Aaron

  • Hey Aaron, thank you for your endeavor!

    Thank you for the explanation of the filter and sink/source currents, that makes sense!


    Without testing maybe it’s hard to say where to place the ground connection resistor, I will just try it.

    I’m not sure if this answer from you:

    Aaron said:
    The more ground you can allocate for power ground and the DRV8300 ground, the lower the inductance will be. A good strategy is to place the power ground pour on that side of the board, repeat that pour across multiple layers, and use stitching vias to connect the grounds together with the stitching vias. Then connect the power ground to the logic ground either at the top or bottom using the 0-ohm resistors.

     

    relates to my last question:

    Daniel said:
    A completely different idea would be, to put the DRV8300 on the power ground like in the picture below and connect them anywhere in the green rectangle. What do you think of this?


    or if it’s just a good way how to do.

     


    Now I have really redrawn the DRV part and put it on the power ground:

     

    It looks good to me too. I will order both versions (DRV on logic and power gnd) because I would like to know if I can measure/see any differences. I will tell you how it went when I’m done.

     

     

    Thanks, you helped a lot,
    Daniel

  • Hi Daniel,

    I think what you have shown in the attached picture is good. I would prefer DRV8300 on power ground so thermal pad has better dissipation and the ground is shared with gate current paths, rather than digital signal paths. But I have seen both methods from customers and they have all had varying levels of performance. 

    Thanks,
    Aaron

  • Hey Aaron, thank you for your input.

    I’ve thought about it and it seems to me the version with the DRV on power gnd is the better one. Especially because of the reasons you already mentioned - and the impedance of the return path from the gates.
    I will order the version where the DRV is on the power gnd.

    Thank you,
    Daniel

  • Hi Daniel,

    Good to know, let us know if you have any questions once you receive your PCB. May I close this thread?

    Thanks,
    Aaron

  • Hello Aaron, yes you can close this thread.

    Best Regards,
    Daniel

  • Thanks for the confirmation!