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DRV8353: Fault triggered at 160N load

Part Number: DRV8353
Other Parts Discussed in Thread: CSD18532Q5B, DRV8323,

Hello experts,

I have a custom motor control board with a DRV8353RSRGZR driver to control a 57BLR70-24-02 motor in order to lift up different weight.

When the load is under 160N the motor can lift it up with no problem (example: supplied with 10%PWM, the motor can lift a 120N load up) and the motor phase looks like this

But whenever I try to lift up heavier loads like 160N, 200N etc.. even setting up more PWM duty cycle, the driver nFault pin is asserted low and the VDS_HB and VDS_LC are set in the Fault Register 1.

Here are phase currents shown when the motor is stalled and before I disable the driver to check for Fault Registers

1V = 1A

I don't understand this behaviour.

I can provide

SPI config : 

Register => Config 

0x02 => 0x41

0x03 => 0x3EF

0x04 => 0x7EF

0x05 => 0x364

0x06 => 0x243

0x07 => 0x0

Mosfet used : CSD18532Q5B 

Motor used : www.omc-stepperonline.com/.../24v-3500rpm-0-47nm-172w-10-4a-f57x69mm-moteurdc-
sans-balais.html?search=57BLR70-24-02

  • Hi Sebastien!

    Thanks so much for providing the FET part number and a link to the motor. 

    The team and I will take a look at your settings and application and respond to you by the end of the day Monday.

    Thank you!

    Tyler McCulloch

  • Hi Sebastien,

    Thank you so much for your patience!

    Based on the provided information, we know that an overcurrent condition is occurring when the DRV is driving heavier loads. The faults indicate the voltage drop across external MOSFET RDS(on) is larger than the VDS_OCP threshold for longer than the tOCP_DEG deglitch time. In order to increase the acceptable current limit through the FETs, we must increase the VDS_LVL setting via SPI. By increasing this value, we allow a larger voltage drop across the external MOSFET RDS(on) resistor, thus allowing more current through the system.

    As a side note, I noticed you are turning on the FETs in your system very quickly. Based on the settings provided, it looks like the FETs are being turned on/off in less than 10ns. I would highly recommend lowering your IDRIVE settings so that the FETs are not switching on/off faster than 100ns. We have seen damage to FETs and unintentional gate coupling in the past because of fast gate slew rates. I would recommend lowering IDRIVE to around 50 mA for source which will give around a 100ns for rise time.

    Let me know if this solved your issue. Please reach out if you have any more questions/concerns! 

    Tyler McCulloch

  • Hello Tyler,

    Thank you for your advise and reactivity.

    I've applied the changes you've advised me (IdriveP = 50mA, IdriveN = 100mA, OCP_DEG = 8µs, VDS_LVL = 1.5V) , but with no success.

    The result is still the same, the motor doesn't lift the load and a VDS_LC always occurs.

    I know that this motor can lift this load because I have a previous board with the same FETs and a DRV8323 running the same application and I never had this kind of fault. With the previous board (same config that I have applied on DRV8323 and DRV8353), the motor lifted almost 400N, way more than what I can here..

    Let me know if you need some extra info to better understand the case.

    Thank you!

  • Hello Sebastien,

    I'll consult with my team on this issue and get you a response by the end of the day Monday. 

    In the meantime, could you provide us with two waveforms and answer some questions:

    1. Differential voltage between VDRAIN and SHx - waveform
    2. Voltage across Rsense (and the value of Rsense) - waveform
    3. What is VM in your application?
    4. What PWM frequency and duty cycle are you using?

    Thanks!

    Tyler McCulloch

  • Hi Tyler, 

    The VM is 42V in my application and the PWM frequency is 40KHz.

    The duty cycle depends on the load I'm lifting up but from 160N load I get the Fault flag from a duty cycle of 15%. If i set a lower duty cycle (say 10%) I can't lift the load but no fault is reported by the driver

    You'll find below the waveforms you've asked for:

    Here is Vrsense C (Yellow) and Vrsense A (Blue)

    Rsense = 0.001ohm

    Vdrain (red) - VshA (blue)  from the motor spinnig to where it gets stuck

    Vdrain (red) - VshB (blue) from the motor spinnig to where it gets stuck

    Vdrain (red) - VshC (blue) from the motor spinnig to where it gets stuck

    Hope you'll find what's wrong and could help me fix it.

    Thank you!

  • I can give you also the details of the application schematic:

  • Hi Sebastien,

    Thanks so much for providing waveforms!

    The team and I are going to review the schematic you provided along with the attached waveforms. We aim to provide a response to your issue by the end of the day Tuesday.

    Thanks!

    Tyler McCulloch

  • Hi Sebastien,

    Thank you for your patience.

    Could you monitor the FET gate waveforms during motor operation? Based on board layout and the PWM switching, sometimes the high and low side gates can couple together and inadvertently cause both FETs to be on at the same time. This will cause a shoot-through event which could trip the OCP system.

    Since the fault flags keep appearing on the high side FET on phase B and low side FET on phase C, please monitor those pins on an oscilloscope during motor operation. Triggering on nFAULT going low would be excellent.

    Thank you!

    Tyler McCulloch

  • Hi Sebastien,

    Do you need assistance on this thread? If not, please mark as "Resolved". 

    Thanks,
    Aaron

  • Hello Tyler,

    Thank you for your help and sorry for the late answer. I work with Sebastien, I monitored the gates on the high side FET on phase B (Blue) and on the low side FET on phase C (yellow). 

    It is triggered on nFAULT going low.

    Thank you,

    Martin Rys

  • Hey Martin,

    Thank you for providing the waveform. I will consult with the team and aim to provide feedback by early next week.

    Best Regards,

    Akshay

  • Hey Martin,

     

    The waveforms are too zoomed out to make observations and draw conclusions, so would it be possible to provide the following 4 waveforms on the same screen: nfault, SHB, GHB, and Vdrain. This would let us see the trends as nFault is pulled low. I would recommend a 25us/division setting so that the waveform is a bit more zoomed in.

     

    Best Regards,

    Akshay