This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8718-Q1: Questions about WATCHDOG/OOL and OSC

Part Number: DRV8718-Q1

Hi team

My customer is using DRV8718SQRVJRQ1 on a new project and they met some problems during the prototype test, could you help give your comments? 

1. What is the recommended watchdog fault recovery process?

The customer found only the following process #1 is valid to clear the watchdog fault and enter a normal operation, for #2 the first invert WD_RST bit is valid but the second invert WD_RST bit is failing and the device would report a watchdog fault.

#1: WD_EN=0b --> CLR_FTL=1b --> WD_EN=1B --> Invert WD_RST bit every 83ms.

#2: CLR_FTL=1b --> Invert WD_RST bit every 83ms

2. OOL and OSC

8.3.8.12 give the introduction of OOL and OSC feature but what is the working principle and when to enable these two features? There is also no a truth table shown, could you elaborate it more?