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DRV8343-Q1: OCP

kura
Genius 4680 points
Part Number: DRV8343-Q1
Other Parts Discussed in Thread: DRV8343S-Q1EVM

Our customer has questions about DRV8343SPHPRQ1.

<Question>

The overcurrent is detected by the OCP function of the driver IC, but when the power supply of the driver IC drops (voltage enough to generate ULVO), does the overcurrent threshold of internal OCP drop ?

OCP has both VDS_OCP and SEN_OCP set.


<Background of this question>
OCP occurred when the power supplied to the driver IC was momentarily dropped (about 5.5V to 6.5V) during motor evaluation at the customer's site,with a current value that was not the original set current.

UVLO was sometimes occurring when OCP occurred. 

This voltage drop was due to the current limitation of their DC power supply, but they wants to know if the voltage drop makes OCP more likely. 

<Conditions at the time of occurrence>

OCP occurs when the brushless motor is rotated and the power supply voltage drops to 5.5V to 6.5V.

Power supply voltage: Set value DC14.5V

When the motor rotates, it drops to about 5.5V to 6.5V when the current flows due to phase changing.
FET on resistance:1mohm
Shunt resistance:1mohm
Current value:Peak 70A
VDS_OCP setting value:0.26V
SEN_OCP setting value:0.25V

Please advise us.

Regards,

Kura

  • 0
    TI__Mastermind 26046 points

    Hi Kura-san,

    I'll look into your request and get you a reply by tomorrow. 

    Thanks,
    Aaron

  • 0 in reply to Aaron Barrera
    TI__Mastermind 26046 points

    Hi Kura-san,

    Sorry for the delay in reply.

    kura said:

    The overcurrent is detected by the OCP function of the driver IC, but when the power supply of the driver IC drops (voltage enough to generate ULVO), does the overcurrent threshold of internal OCP drop ?

    OCP has both VDS_OCP and SEN_OCP set.


    <Background of this question>
    OCP occurred when the power supplied to the driver IC was momentarily dropped (about 5.5V to 6.5V) during motor evaluation at the customer's site,with a current value that was not the original set current.

    UVLO was sometimes occurring when OCP occurred. 

    This voltage drop was due to the current limitation of their DC power supply, but they wants to know if the voltage drop makes OCP more likely. 

    The internal VDS_OCP threshold should remain in the min/typ/max specs as long as VM > UVLO. This is confirmed by characterization data, regardless the VM value, the VDS_OCP threshold lies within the datasheet specs.

    If the customer wants a confirmation of this, next week I can test on the DRV8343S-Q1EVM if there is any variation to the VDS_OCP threshold at different VM values. 

    kura said:

    OCP occurs when the brushless motor is rotated and the power supply voltage drops to 5.5V to 6.5V.

    Power supply voltage: Set value DC14.5V

    When the motor rotates, it drops to about 5.5V to 6.5V when the current flows due to phase changing.
    FET on resistance:1mohm
    Shunt resistance:1mohm
    Current value:Peak 70A
    VDS_OCP setting value:0.26V
    SEN_OCP setting value:0.25V

    When testing these settings, can you confirm that the best possible MOSFET switching is occurring by adjusting the IDRIVE value so VDS slew rate is not faster than 100ns? Just want to ensure VDS is not triggered by shoot through current from large dV/dt coupling. IDRIVE < Qgd of FET / 100ns. 

    Thanks,
    Aaron

  • 0 in reply to Aaron Barrera
    Genius 4680 points

    Aaron-san

    Thank you for your support. Sorry for late response.

    Customer wants confirmation of this, Please test on the DRV8343S-Q1EVM if there is any variation to the VDS_OCP threshold at different VM values.


    Regarding the IDRIVE value you asked about, it is as follows, and they think there is no problem, but please check it.

    Only the high side is PWM controlled, and the low side is ON/OFF controlled,
    The high side is slowed down to prevent the low side from turning ON when the high side is ON.
    ・IDRIVEP_H: 0111b (65mA)　
    ・IDRIVEP_L: 1000b (200mA)
    ・Qgd: 14.4nC (typ)

    【question】
    A 1Ω resistor is mounted between GHx, SHx, GLx, DLx, SLx and FET,
    Will this affect this event?

    Also, if you have any suggestions, such as there is no problem with mounted resister  or it is better not to mounted resister, please let us know.

    Regards,

    Kura

  • 0 in reply to kura
    TI__Mastermind 26046 points

    Hi Kura-san,

    kura said:
    Customer wants confirmation of this, Please test on the DRV8343S-Q1EVM if there is any variation to the VDS_OCP threshold at different VM values.

    I will try and get this test complete before end of the week. 

    kura said:

    Regarding the IDRIVE value you asked about, it is as follows, and they think there is no problem, but please check it.

    Only the high side is PWM controlled, and the low side is ON/OFF controlled,
    The high side is slowed down to prevent the low side from turning ON when the high side is ON.
    ・IDRIVEP_H: 0111b (65mA)　
    ・IDRIVEP_L: 1000b (200mA)
    ・Qgd: 14.4nC (typ)

    I do not have concern about the IDRIVE values implemented above.
    However, because only high-side PWM is implemented, I am assuming low-side is OFF, which is asynchronous modulation for the phase current. So VDS overcurrent will not be implemented across the low-side MOSFET of the driving phase. 

    kura said:
    A 1Ω resistor is mounted between GHx, SHx, GLx, DLx, SLx and FET,
    Will this affect this event?

    I would make sure that the voltage at the FET at the pin is the same to ensure there is not a voltage drop across the 1ohm resistor. Ideally this should be 0-ohm resistor for SHx/DLx/SLx. Not sure what is meant by "FET". Can you share schematic?

    1 ohm resistor on GHx/GLx is okay because series gate resistance helps limit gate current if needed. 

    For instance, make sure the SHA voltage at the FET is the same at the SHA pin. If there are different voltages, then voltage is being dropped across the 1-ohm resistor and this can affect VDS overcurrent measurement. 

    Thanks,
    Aaron

  • 0 in reply to Aaron Barrera
    TI__Mastermind 26046 points

    Hi Kura-san,

    For VDS_OCP setting value = 0.26V, here is six-sigma threshold variation at different VM values:

    VM = 5.5V:

    0.261V to 0.275V

    VM = 24V:

    0.261V to 0.275V

    VM = 60V:

    0.271V to 0.289V

    Thanks,
    Aaron