Other Parts Discussed in Thread: DRV8307
Hi all
Would you mind if we ask DRV8308?
Could you let us know the LOCKn assert condition(LOCKn=Low)?
The datasheet shows "After a constant speed is reached, the LOCKn pin is pulled low and only one Hall sensor becomes used; " only.
As the background of this question, at the our customer site, there are following situations;
-CLKIN=300Hz, FGOUT=300Hz -> LOCKn assert
-CLKIN=300Hz, FGOUT=70Hz -> (after a certain time) -> LOCKn assert
So, it seems that LOCKn assert is not relation between CLKIN and FGOUT.
After FGOUT value becomes constant, LOCKn asserts.
Kind regards,
Hirotaka Matsumoto