Hi,
DRV8711 is used to drive a stepper motor; the VM voltage is 24 VDC. APDF/BPDF was detected when the motor was driven.
Conditions for APDF/BPDF.
・Whether or not the gate-source voltage exceeds 1 V 2.2 us after the current is sourced to turn the FET ON.
・Whether or not the gate-source voltage is below 1 V 2.2 us after sinking the current to turn the FET OFF.
It is our understanding of the above two points, but no abnormality was found when the gate waveform was observed.
Referring to 8.1.2 Optional Series Gate Resistor in the data sheet, it is stated that as a countermeasure against APDF/BPDF false detection, a series resistor of 47 to 120 Ω should be placed between the Low side driver output and the FET gate, and the Dead time should be set to the maximum value of 850 ns. The description says to drive the device with a series resistor of 47 to 120 Ω between the Low side driver output and the FET gate.
So we added 120Ω to the Low side and set the Dead time to 850ns. When I set the Dead time to 850ns by adding 120Ω to the Low side, APDF/BPDF occurs rarely.
Q1. Only the Low side has a series resistor and the High side is set to 0 Ω. Is it necessary to add a 47 to 120 Ω resistor to the High side as a countermeasure against APDF/BPDF false positive detection?
Q2. Are there any other conditions other than those mentioned above under which the APDF/BPDF is judged to be APDF/BPDF?
Thanks,
Conor
