Hello
According to the datasheet DRV8328 devices have a nSLEEP pin which not only act as sleep but also as fault reset input. Let me quote the datasheet here:
If the user wants to put the device into sleep state after latched fault event, the inputs INHx and INLx needs to be pulled low prior to driving the nSLEEP pin. If the inputs INHx and INLx are not driven low, then the fault is reset after nSLEEP is driven low for the tRST time and there can be pulses on gate driver outputs GHx and GLx prior to device entering sleep. The duration of pulses on GHx and GLx can be of duration tSLEEP if INHx and INLx are not pulled low.
Is this true for both, the 6x and 3x PWM variants of the chip? It seems redundant to me that INHx needs to be driven low when INLx already acts like an "enable" pin?
Thanks