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DRV8328: DRV8328 Fault Reset

Part Number: DRV8328

Hello

According to the datasheet DRV8328 devices have a nSLEEP pin which not only act as sleep but also as fault reset input. Let me quote the datasheet here:

If the user wants to put the device into sleep state after latched fault event, the inputs INHx and INLx needs to be pulled low prior to driving the nSLEEP pin. If the inputs INHx and INLx are not driven low, then the fault is reset  after nSLEEP is driven low for the tRST time and there can be pulses on gate driver outputs GHx and GLx prior to device entering sleep. The duration of pulses on GHx and GLx can be of duration tSLEEP if INHx and INLx  are not pulled low.

Is this true for both, the 6x and 3x PWM variants of the chip? It seems redundant to me that INHx needs to be driven low when INLx already acts like an "enable" pin?

Thanks

  • Hi Vincent,

    I believe what you quoted from the datasheet seems to give directions if you wanted to put the device into sleep after a latched fault event (meaning without sending a Reset Pulse). In this case without driving INHx and INLx low there could be unwanted outputs on GHx and GLx as you are trying to put the device into sleep.

    Is this true for both, the 6x and 3x PWM variants of the chip?

    There doesn't seem to be any documentation in the datasheet that mentions different instructions for the PWM modes in regards to this specific scenario so yes this would be true for 6x and 3x PWM variants. This makes sense because 3x and 6x have similar truth tables when INHx and INLx are low, making this compatible for both PWM modes.

    Regards,

    Yara

  • No offense, but this is an unsatisfying reply. That the 3x PWM variant can have "unwanted outputs" on GH and GL without driving INH and INL low is simply wrong. INL acts like an enable input and as long as it is driven low the gates will be driven low no matter what state INH is in. Therefor I disagree that having to drive both inputs (INH and INL) low makes sense...

    I was hoping that the data sheet was imprecise at this point and that a TI employee could explicitly confirm or rule this out.

  • Could you elaborate on why you would need this information so I can provide feedback to the team? Are you trying to use 3x PWM while keeping INLx high and put the device in sleep right after a fault?

  • My application would have kept one of the INH pins high all the time. If this results in fault conditions being reset after wake up though I'd make INH switchable.

  • Hi Vincent,

    I discussed your issue with my team, it seems for this feature to work correctly really the most important thing would be to ensure that the inputs are not switching when you are attempting sleep after fault without clearing. It's not guaranteed these steps will perform properly without INHx and INLx driven low on 3x PWM mode (since it is not explicitly stated in the datasheet) but it's definitely worth testing.

    My team and I would also like to know why you want to keep INHx high all the time?

    Regards,

    Yara

  • Thank you, I'll make INH switchable then.

    I would like to generate a square wave signal with the chip, e.g. by switching INHA and INHB alternately. This could be achieved with an external NOR gate, i.e. INHB = !INHA. But then you could never switch off both pins at the same time.

  • Hi Vincent,

    Our team is currently out of office due to US holidays, and will be returning next week.
    Please anticipate a delayed response to your question - and feel free to share additional details which may be helpful to the analysis in the meantime.

    Best Regards,
    Andrew

  • Hi Vincent,

    Thanks for sharing and clarifying why you wanted to keep INHx high, I'll relay this information to the team and see if it warrants revisions or additional documentation. I'll be closing this thread, feel free to post another E2E for any additional questions.

    Regards,

    Yara