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DRV3245Q-Q1: SPI configuration register reset during EN cycle

Tamas Federer
Prodigy 10 points
Part Number: DRV3245Q-Q1

Hello,

I was not able to find any information in the datasheet of the component if the SPI configuration registers are getting resetted during an EN cycle.

Example:

  • Device is powered and configured
  • EN is set to TRUE
    • Registers are correctly set
  • EN is set to FALSE
  • EN is set to TRUE
    • Will the registers be resetted?

Thank you in advance!

  • 0
    TI__Guru 63280 points

    Tamas,

    Per the datasheet, the device is in sleep mode when EN is set low:

    The AVDD and DVDD regulators are controlled by the EN signal, once it is set low the regulators shut down and the device register map is returned to default. The device will need to be reprogrammed over SPI after EN is taken high again.

    What is the timing for the EN signal here? Can you share the timing of this signal being high and going low?

    Regards,

    -Adam

  • 0 in reply to Adam Sidelsky
    Prodigy 10 points

    Hello Adam,

    Many thanks for the quick feedback!

    In our application we set the EN signal to LOW for ~20ms before it's going to HIGH again. We did some testing, and we've seen that the registers are getting resetted even with a 1ms LOW-HIGH EN cycle.

    Anyhow, your explanation is clear and now we have an explanation of this behavior.

    Thanks again!

    Best,
    Tamas