DRV8714-Q1: DRV8714-Q1

Hey Darshan,

Se the BRG_MODE bits to 0b10

BRG_MODE is in IC_CTRL1, so to spin the motor you'll need 

• EN_DRV=1
• EN_OLSC=whichever, 0
• BRG_MODE=10
• LOCK=011b (unlocked)
• CLR_FLT=whichever, 0

Thus IC_CTRL1 = 0b10100110

Do you have an EVM? This will be the easiest way for you to learn the register config for everything you want.  https://www.ti.com/tool/DRV8714S-Q1EVM 

Best,

Jacob

Hi Jacob ,

I have sent the below msg , but H brig not working 

IC_CNTL1 Reg: 0x07 0x97 

IC_CNTL1 Reg: 0x07 0x96 

My question to you is 

• LOCK=011b (unlocked) 
• 
• Does the H-BRIDGE work for any other combination of lock bit . 
• like : 001,100,010????
• IC_CNTL1 Reg: 0x07 0x95 ???.
• Can we have call please , i have too many questions to ask , this thread will not be sufficient :)

Darshan,

Is this your own board or the EVM?  Please test it out on the EVM to rule out hardware issues.

And can you verify your SPI format follows the device requirement? Typically this is called SPI MODE 1.  

Best,

Jacob

Basically try to confirm your SPI communication is working in general - try Writing to a register then Read it back, you should see your Written changes on the register 

Hi Jacob , 

I m working on our own design not on dev board  , which is as that of application ckt ,

to check SPI  , i m using chip id : 0x00 0x40 .

response is : 0xC0 0x40 . (spi is works ) 

My concern is on activating H bridge . 

if the lock bit is set 010 will that work ?? 

data sheet has the information :011 and 110 . 

Hey Darshan,

Okay that means that your SPI READ is working, but you need to test SPI Write.  Try writing to a setting register and read it back.  You shouldn't have to write to the Lock bit at all since the bit is set to UNLOCKED by default

Best,

Jacob

Hi Darshan,

As well as be sure to check if nSCS is set to HIGH after the register write SPI transaction. The rising edge on nSCS is required to latch in the written data. Reads may be kay in this case. In general nSCS must always return to logic HIGH after every read or write transaction. See below example.

Regards, Murugavel