Other Parts Discussed in Thread: DRV8305
Tool/software:
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Tool/software:
Adam-san
Thank you for your reply.
The customer's intention is to confirm whether the outflow current from the VDRAIN terminal is below the rated value when a negative surge is applied.
(Since the rated voltage on the negative side is -0.3V, the customer is considering verification with current.)
Regards,
kura
Hi Kura,
The maximum sourcing current of the 45V max VDRAIN pin is not explicitly given, however we do recommend adding a 100Ohm current limiting resistor to protect the source pin, which could set an upper limit of nearly 450mA. I would recommend experimentally testing this current capability with this in mind and caution against sourcing too much current in this test.
I hope this information is helpful, and please reach out further with any additional questions.
Best Regards,
-Joshua
Joshua-san
Thank you for your support.
We got additional questions from customer. Please give us your advice.
1.about Gate drive fault
I understand that if the gate voltage does not rise during TDRIVE, a gate drive fault signal is issued, but how is this judged?
(Is it until the gate voltage has fully risen? Or is it enough if it exceeds a certain threshold voltage?)
2.about High side gate potential and source potential at power-on
When power is turned on, the potential of the high side gate(GHx) and source(SHx) are at the power supply voltage level of the pre-driver.
The gate input from the microcontroller (INHA,INLA,INHB,INLB,INHC,INLC) are Low, but is any processing being performed in the internal circuit of the gate output part of the pre-driver?
regards,
Kura
Hi Kura,
Thank you for the reply and additional questions-- please allow me to respond to them within the next day.
Best Regards,
-Joshua
Hi Kura,
1.about Gate drive fault
I understand that if the gate voltage does not rise during TDRIVE, a gate drive fault signal is issued, but how is this judged?
(Is it until the gate voltage has fully risen? Or is it enough if it exceeds a certain threshold voltage?)
The driver checks if the gate voltage is fully on and the MOSFET is conducting during the TDRIVE time, and if the gate is not on fully by the end of TDRIVE timing, then a GDF is thrown.
2.about High side gate potential and source potential at power-on
When power is turned on, the potential of the high side gate(GHx) and source(SHx) are at the power supply voltage level of the pre-driver.
When both the highside and lowside of the phase is off (INHX=INLX= 0V) then leakage from SHx will conduct through the body diode up to the supply voltage, and GHx will follow SHx.
This is normal/expected behavior, and this E2E FAQ explains the phenomenon further:
Hope this response has been helpful.
Best Regards,
-Joshua
Joshua-san
Thank you for your support.
Our customer has additional question
About the IC clock:
When conducting EMC testing, the noise level becomes high at around 2.5MHz.
This decreases significantly when the pre-driver power is turned off.
Are there any internal clocks in the DRV8305 that run at around 2.5MHz?
They are aware of the 58MHz internal clock and the charge pump clock that can be selected via a register.
Please advise us.
Regards,
Kura
Hi Kura,
I'm glad to provide continued support.
I am only aware of the onboard LDOs (AVDD, DVDD, and VREG) that may contribute to EMC, but I'm not familiar currently with any peaks to a 2.5MHz EMC peak. Does the customer notice any associated harmonic peaks of this 2.5MHz signal?
And can you help to clarify how this signal was reduced when EN_GATE is enabled/disabled and when WAKE (pin) is enabled/disabled? This will help us to narrow down the possible sources of EMC from the device.
Best Regards,
-Joshua