DRV8889-Q1: what is the CPOL and CPHA of our device

Hi Bengi,

Please refer to the following section in the datasheet. I've highlighted two bulleted lines and translated that to the corresponding CPOL and CPHA for the SPI transactions. CPHA = 1, you can also see the capture point is the falling edge of the SCLK in the figure from the datasheet you shared.  

See below an actual capture of a transaction between MCU and the DRV8889-Q1 using a logic analyzer.

Regards, Murugavel

Hi Murugavel,

Thanks for your quick reply. Another question is:

What is the meaning for below five timing parameters? Customer wants to know the time cost for one step.

BR,

Bengi

Hi Bengi,

The first three are for STEP input signal. The next two for DIR input signal. See below diagram with the labels 1 to 5.

Although the digital input for STEP input may be able to support up to 500 kHz. The actual upper limit will be limited by the system, stepper motor L and R, VM voltage and target IFS. Usually it is around 100 kHz at 256 uSteps. 

Regards, Murugavel

Hi Murugavel,

Customer now is considering the control method for STEP and DIR. The two methods are:

1. Use SPI to write related register. SCLK 1MHz.

2. Use MCU GPIO to control 8889's DIR and STEP pin. They want to use interrupt timer to control this, timer period 0.7ms.

Customer wants to know which way is more effective (has faster respond) and why. Because there exists some delay in SPI timing, customer wonder the response time between sending command to one step.

BR,

Bengi

Hi Bengi,

Using MCU GPIO with a fixed interrupt Timer period based output for STEP input would be the preferred method. This would be consistent STEP to STEP period which is important for stall detection function to work. If there is variation between STEP pulse periods stall detection will not work. If SPI control is used there will always be some variation between STEP to STEP pulse timing. Also GPIO would the best way to use with minimum MCU resource.

Regards, Murugavel