The TI E2E™ design support forums will undergo maintenance from July 11 to July 13. If you need design support during this time, open a new support request with our customer support center.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8955: Difference Between Packages and Output Paralleling

Part Number: DRV8955

Tool/software:

Hello,

While working on my design using the DRV8955, I noticed that the package for PWP and RGE differ slightly.

It seems that the PWP has two pins per output. I was just wondering why that was.

And to follow up - when using the MODE pin to adjust between the amount of solenoids being driven, are the pins paralleled internally or am I required to short them external to the chip? I would like to test multiple configurations and do not want to short it externally if I do not have to in order to reduce the amount of PCB revisions I do.

Regarding the H-bridge configuration, would I just be connecting the load between two OUTx pins?

Thanks in advance.

  • Hi Sam,

    It seems that the PWP has two pins per output. I was just wondering why that was.

    This is because PWP package has 28-pins vs. 24-pins for the VQFN package, we took advantage of the extra 4 pins. The VQFN would have two bond wires internally. There's no trade off with drive capability. However the PWM has lower thermal resistance so offers better power dissipation. 

    And to follow up - when using the MODE pin to adjust between the amount of solenoids being driven, are the pins paralleled internally or am I required to short them external to the chip?

    You have to short them externally. See below table from the datasheet.

    Regarding the H-bridge configuration, would I just be connecting the load between two OUTx pins?

    Yes, this is correct. 

    Regards, Murugavel 

  • Thank you very much!