DRV8305: no output with lower OCP and charge bump, VCPH, PVDD UV issues

Hi Lee, 

Thank you for posting to our forum! 

From the information provided I do believe a schematic review is appropriate.  And to keep this communication on the forum can you send the schematic file directly to me through E2E private messaging?

Best Regards, 

-Joshua

Hi Joshua,

Nice to get your requirement, and I already sent the schematic file to your email address, kindly pls have a check.

Looking forward the further communication, thanks.

Best Regards, 

-Easy

Hi Easy, 

Thank you for the response.  I have checked my email and the E2E forum but have not received any documents yet. Can you help to resend them or try a new method?

Thank You and Best Regards,

-Joshua

Hi Joshua,

Okay, got it, I just resent the file to you by previate messaging through E2E forums, kindly pls have a check.

Hopefully, it can work well, thanks.

Best Regards,

- Easy

Hi Easy, 

I received the file, thank you! 

Please allow me to review it this week and follow up the start of next week with any comments/suggestions. 

Thank You and Best Regards,

-Joshua

Hi Easy, 

Can you observe the device behavior when VDS_LVL OCP is disabled( 50% and 100% duty cycle, 20kHz PWM)? There does not appear to be a schematic-related source to this issue, but I would like to confirm the instance these faults occur -- If you could measure the nFAULT signal, GHx, and VCPH on the same waveform during this fault occurrence that would be very helpful for overview. 

Best Regards,

-Joshua 

Hi Joshua,

Thanks for team's peoposal, we executed the testing cases under the condition of ignoring OCP function, kindly pls find the report enclosed significant signal pictures. By the way, the PDF file includes overall content.  

We sincerely hope it can help team to review, thanks.

Best Regards,

- Easy

Drv8305 stay OCP nfault - Disable OCP function[EN for TI] V03.pdf

Hi Easy, 

Thank you for this detailed test information! This will really help in my and my team's review as we work to resolve this matter. Please expect a further reply before the end of this week. 

Best Regards,

-Joshua

Hi Easy, Thank you again for the information. 

I have an observation regarding the SHx and GHx waveforms-- it appears when the gate waveforms (CH2) turn on the actual voltage doesn't rise to 10V above SHx (they appear to be at the same potential) and the nFAULT trips at the same time, is that correct with what has been measured? 

It also appears that the Charge Pump is 10V above GHX, can you measure GHx/VCPH with respect to SHx instead of to GNDto better help this understanding? It seems as of now that the VCPH UVLO is falsely tripping. 

Best Regards,

-Joshua

Hi Joshua,

Okay, we have received requirement on measuring GHx/VCPH with respect to SHx instead of to GND. Unfortunately, we do not have an isolated probe on hand, so it may take several days to purchase one and provide a report by then. We are still checking the PCB layout and components around the DRV mutiple times for troubleshooting, almostly refer to the last design of TLE9XXX well-tried case and DRV’s DS.

While trying various SPI settings and other PWM inputs, unexpectedly, a DRV was burned with staying very hot and the power supply voltage dropped sharply within a few seconds. This prevents us from implementing any DOE again without convincing indication.

I would like to share the PCBA layout diagram with you and TI mentor, and convey the files by previate message. Kindly please have a review, any suggestion is welcome.

Thanks a lot.

Best Regards,

- Easy

Hi Easy, 

Thank you for the update.  

Do you have a record of what settings were used when the device experienced this new failure?

And I have received your direct message with the layout and will begin a prompt review! Please expect a further response/feedback before the end of this as I look into this matter.  

Best Regards,

-Joshua

Hi Joshua,

Thank you for taking up a lot of your time on the layout.

The possible settings of DRV breakdown is attached here for reference. Currently, there are still 2 pieces of new boards available for debugging. We suspect that the gate resistance setting is unreasonable, resulting in excessive current and the charge pump not being properly applied to it. If removed the 22Ω resistor or , will it be effective or not?

Best Regards,

- Easy

Hi Easy, 

I'm always happy to be able to help out,, so worries there. Please look forward to the layout feedback. 

Thank you for getting this additional information as requested. 

Easy Lee said:

We suspect that the gate resistance setting is unreasonable, resulting in excessive current and the charge pump not being properly applied to it. If removed the 22Ω resistor or , will it be effective or not?

I believe this to be a valid concern,  and this could be measured by observing any discrepancies/differences in the switching speed (turn on/off time) of each parallel FET, as a current imbalance and excessive draw could be overworking the charge pump and it's supply capacitor. 

Can you observe the behavior with 1. The 22 ohm resistor removed and 2. The parallel FETs removed (if possible) 

This could further help narrow down the root cause and get closer to a successful resolution. 

Thank You and Best Regards!

-Joshua

Hi Joshua,

As our last discussion on the 22Ω resistor and FETs, we removed the gate resistor and diode, and DRV still reported a fault throuth the status register, but the error state changed from overcurrent or charge pump undervoltage to VGS drive fault, eithor low side or high side. The voltage signal and waveform are similar to before, without significant changes.

By the way, the isolation probe is on the way and it is expected to recive tomorrow, and then we will test it.

Thanks a lot.

Best Regards.

- Easy

Drv8305 stay OCP nfault[EN for TI] V04 2024Oct30.pdf

Hi Easy, 

Thank you for your reply.

This is interesting as we can see the lowside VGS voltage slowly decreasing (most likely resulting in the new fault. This does appear to support the lowside VGS regulator is struggling to drive the current mosfet selection.  

Can you try this exact same setup but using the lowest IDRIVE settings? (the slowest switching speed with the gate current to better show if the VGS drive is more stable when working less in this configuration).

Best Regards,

-Joshua

Hi Joshua,

Following your suggestion, we restored the same testing scenario and set IDRIVE from the minimum value 10mA, gradually increasing it to 500mA. Based on the collected waveform, we can observe a regular where the voltages of GH and SH gradually increase insequence.

Furthermore, we also nervously set the maximum value 1000mA once, and DRV still reported the same error, but the oscilloscope failed to capture it by its trigger funtion, so there is not screen shoot available here.

Best Regards.

- Easy

Drv8305 stay OCP nfault[EN for TI] V05 2024Oct31.pdf

Hi Easy, Thank you for the new testing info... 

I'm still looking into best next steps and appropriate updates to the PCB that may help this behavior. 

Please expect this response tomorrow. 

Best Regards,

-Joshua

“It also appears that the Charge Pump is 10V above GHX, can you measure GHx/VCPH with respect to SHx instead of to GNDto better help this understanding? It seems as of now that the VCPH UVLO is falsely tripping. ” - Joshua

Hi Joshua

According to your request, we have purchased differential probes and implemented tests today,  kindly please refer to the signal report below. Unfortunately, the oscilloscope failed to capture the waveform when setup GHx respect to SHx.

Best Regards.

- Easy

Hi Joshua

Thanks for your response and question.

From this waveform am I correct reading that the "multiplied by 5 times" is saying that this 2V/div value is actually 10V for VCPH-SHx? --Joshua

Re: right, it means voltage value jumps from 10V to 20V in the wavform of VCPH-SHx

For proper operation we should see that VCPH-PVDD  = PVDD+10V, and that GHx is pulled up to PVDD+10V when INHx is high. So this value of ~10V - SHx should be sufficient if it matches to PVDD - 10V. Can you verify that the difference between GHx/VCPH - SHx >= 10V and that PVDD is not decreasing/dipping? This again may help to point to the cause of the UVLO on the device gate driving sources. --Joshua

Re: Based on the observation of the waveform, VCPH is normally around 20V, but GHx is only equal to PVDD, and the 10V of the charge pump is not added to it. This is very strange. If the cause is found, this problem could be solved. We are now trying to investigate the troubleshoot.

Can you also try removing the 10kOhm gate pulldown resistors (R133, R134, R135 and R149, R150, R151).  I believe that these pulldowns may be too strong (10K) that may hinder the driving capability resulting in extra strain on the internal regulators. Typically, if implementing additional gate-source pulldown resistors I would recommend a minimum of 100kOhm resistors, as I believe there to already be internal pulldowns in the DRV8305 device.--Joshua

Re: We can't agree with you anymore, and the pulldown resistors (R133, R134, R135 and R149, R150, R151) have been replaced by 100kOhm resistors, kindly pls refer to reply on Oct. 30th 2024.

Best reard,

--Easy

Hi Easy, 

Thank you for your response.  And I apologize for overlooking the gate-to-source resistor configuration,  so thank you for clarifying. 

I have a team meeting tomorrow to discuss this inquiry,  so I will aim to follow-up by Thursday as I work to help close this.

Thank you for your patience!

Best Regards,

-Joshua

Hi, Joshua,

Thanks for your effort and time on this topic.
This week, we purchased an TI EVM board for DRV8305 and rebuilt both the motherboard and the EVM board using fly wires such as PWM, SPI, Engate, Wake, etc. The verification result is good, with no SPI error except for motor rotation. Until now, we have only noticed that the maximum rated current of the power supply is 2A, which does not meet the requirements of the motor load.
Therefore, the cause of these malfunctions is likely due to the power limitations, and we have urgently purchased a new power supply that can provide 30V and 100A. We plan to conduct testing after receiving the power supply by the end of this week.

Best reagrd,
- Easy

Hi Easy, 

Happy to hear you and your team are seeing better results with these test, and may have found a source to this behavior. 

Please let me know if there is any area I can help with as you begin testing on the EVM with this new supply. 

I look forward to hearing the results. 

Best Regards,

-Joshua

Hi Joshua，

Unfortunately, there is no good news to share with you and TI team.

By now, we have completed a series of comparative experiments on our Mainboard, and executed the validated software, which can drive the motor normally on Mainboard+DRV8305 EVM. There are 3pcs PCBA to be used.
1) Using high current power supply
2) Remove suspicious or non essential resistors and capacitors, etc.
3) Remove all Mosfets
4) Replace with another Infineon Mosfet
5) Replace with a new DRV8305
All experimental results are for VDS overcurrent protection, and if VDS overcurrent protection is disabled, PVDD undervoltage unfervoltage 2 will be reported; If PVDD undervoltage is disabled, Highside charge pump undervoltage will be reported.
Especially, even after removing all Mosfets, these errors are still guaranteed for the first time, and this is very strange.
I saw another relsoved topic on E2E that is very similar to my issues, but the solution is to solder Mosfet,the tile is "
DRV8305: nFAULT active on EN_GATE",kindly please refer to this post as it may inspire us to find a solution.

By the way, our motherboard+DRV8305 EVM can work well with Flywire. If we can identify the differences between our DRV8305 hardware diagram and EVM hardware diagram, it may help us locate the problem. Will TI hardware experts assist?

Best regard,

- Easy

Hi Joshua，

Thanks for your proposal.

In fact, we have torn down all key capacitors around the DRV and measured their value and status to inspect any bug or breakthrough. At the same time, we checked the solder by observing the voltage and re-sodered them by refferring to DRV EVM's schematic diagram. No issue find so far, pls refer to the table below.

About sense resistors, we configure 0.001Ω different from DRV EVM's 0.007Ω or datasheet 0.005Ω, we can get the CSA is around 135A based on TI mentor's calculation in E2E's topic and formualtion in datasheet, so we adjust the gain from 10V/V to 20V/V by SPI configuration, and then the VDS OCP is resolved. However, PVDD undervoltage unfervoltage 2 will be reported; If PVDD undervoltage is disabled, highside charge pump undervoltage will be reported.

We plan to flywire the PVDD pins on the board and connect them to the EVM board for power supply. By this way, the motherboard power supply could be verified if no PVDD undervoltage fault happened.

One DRV8305NPHPQ1 is used on EVM board, but we put  DRV83053QPHPQ1 to use. By researching chapter7.1 in datasheets, we found the VREF/VREG pin should be linked various resistor(+3.3V) and capacitor(GND), so we deal DRV83053QPHPQ1 with VREF/VREG pin linking capacitor (C128-->GND) only as LDO oupupt, without R118-->+3.3V. We double check 3.3v voltage is exactly right there by measuring VREF/VREG pin. Is there any other various configration if we missed, any remind is welcome.

Thanks a lot.

Best regard,

- Easy

Hi Joshua，

When flying one wire from our own board DRV8305 PVDD pin to make power supply for EVM board, DRV can rotate the motor normally, so it can verify the power supply PVDD works well.

Thanks for your attention.

Best regard,

- Easy

Hi Easy, 

Thank you for the update.  Glad to hear that the power supply source is working out well, and this does continue to point to the difference in board design being the source of the issue. 

I'm currently looking over any other differences that could play a role in this behavior we are observing, please expect a more detailed response by tomorrow as I look over your schematic and layout once more.

Best Regards,

-Joshua

Hi Easy, 

After review I do not see many configuration differences, however I would like to ask about these output circuit on each phase: 

I would not expect these to have such a negative effect,  but can you help to test this additional circuitry (if included in the testing already) and see the effect on the device behavior? 

I will let you know if it observe any issues in layout design in the meantime.  

Best Regards,

-Joshua