DRV8714-Q1: RC design of the SP and SN

Hi,

Thank you for your question, Our expert will feedback to you in early of next week.

Hi Ivy,

Please see below the block diagram of the current shunt amplifier. The integrated R_IN are in the gain path of the input amplifier. Any external series resistor will affect the value of the gain as well as if they are not exactly equal will affect the CMRR performance. We do not recommend using external series resistors for SPx and SNx.

Customer can use a capacitor across the shunt resistor if they want without the series resistors. What is the purpose for the RC? The time constant with 10 Ω and 15 nF shown in the customer schematic snippet is very small, about 0.15 us. Given the very low shunt resistor value of some mΩ (not shown by the customer) the small time constant may not be of much use anyways. Thank you.   

Regards, Murugavel 

Hi Murugavel,

Thanks for your comments!

Below are the full schematic of DRV8703-Q1 and DRV8718-Q1.

1. Could you please help review and give further other suggestions?

2. The SDO pin is connected to the MCU's SPI0_SIN and has an external 5V pull-up, the customer's SPI is connected to two SDOs of the DRV8703-Q1 and one SDO in the DRV8906-Q1 in addition to the DRV8718-Q1. Does this design have an impact on the drive of SPI? 

Thanks!

Regards,

Ivy

Hi Ivy,

I assume the FET gates are connected directly as described in the datasheet for these devices.

DRV8703-Q1: nWDFLT pin is an open drain output and required a pull-up resistor. It is an output signal. The netlist on this pin is labeled RESET not sure how the pin is treated. Please clarify. 

Ivy Jin said:

the MCU's SPI0_SIN and has an external 5V pull-up

The SDO of the DRV8703-Q1 is open drain and requires a pull-up. This resistor must support the SPI frequency of operation. What is the pull-up value used to 5V - this is 1k correct based on the DRV8718-Q1 schematic? This is the only device out of these three that requires a pull-up on its SDO. I assume the MCU uses 5 V logic levels. Everything else looks okay.

DRV8718-Q1: Because all three devices SDO are in parallel it must be ensured the nSCS of each of the devices will follow proper timing and will not enabled no two devices at the same time. The DVDD pin has both 1 uF and a 0.1 uF in the schematic. Please use only the 1 uF as recommended in the datasheet. Technically SDO of this device does not require pull-up only the DRV8703-Q1 needs it. We'd recommend this to be close to the SDO pin of the DRV8703-Q1. I assume in-line current sense resistors were used in the FET circuit - not shown.

Regards, Murugavel