Other Parts Discussed in Thread: DRV8316
Tool/software:
Dear TI Experts,
I am encountering a challenge while configuring SPI communication. Based on this lines from the datasheet (page 54 on drv8316 datasheet)
1. "The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high."
2. "Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK pin."
From these two I conclude:
1. CPOL should be set to 0, so that condition 1 is satisfied. This will force the CLK to be low when nCS transitions between low and high.
2. CPHA should be set to 1, so that on the falling edge of the sclk (when data is sampled), the data is stable on the MOSI and MISO lines.
From Wikipedia:
However, looking at the SPI syscfg, I can see 4 SPI modes, non of which are what I'm expecting.
these are the options available there:
As I understand these options, I should select Polarity 0, phase 1, but the the description should be 'Falling edge', not 'Raising edge'. What line is the 'Raising edge' referring to here? clk?
Additionally, when testing all 4 options, I only read values which make sense when selecting Mode 0, which doesn't make sense to me as it does not seem to correspond to the SPI description in the DRV datasheet (at least as I understand it).
Please let me know if you can clarify this.
thanks!
