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DRV2511-Q1: DRV2511-Q1 abnormal output

Part Number: DRV2511-Q1


Tool/software:

Hi Sirs

Question:

1. We input positive voltage PWM signal(0~3V3) to DRV2511 with PVDD 5V => Driver could amplitude normal output from 3V3 to 5V

2. As PVDD 6~18V => Driver will produce impluse waveform instead normal PWM waveform.

    => We confirm the power source to PVDD is abundant.

    => Could you help to solve this issue?

Condition:

1. Driver Ouput: No load

2. Our schematic could be shown as attached.(Follow DRV2511 EVM and Parts)

3. Set up

- FS0, FS1, FS2 = Low

- STANDBY = Low

- Gain = 20kohm to Gnd

 - Reg = 1uF to Gnd

  • 1. Attached is our schematic

    2. PVDD = 5V, Normal Driver Output

    3. PVDD = 6V, Abnormal Driver Output

  • Hello,

    Thanks for reaching out. I have a couple things to try here to find the root cause. 

    Could you monitor the INTZ pin? Does it go low when PVDD is increased to 6V?
    If you decrease PVDD back down to 5V, does it go back to normal opperation?
    If the load is removed does the abornal output still occur?

    Regards,
    Sydney Northcutt 

  • Hi Sydney 

    1. Could you monitor the INTZ pin? Does it go low when PVDD is increased to 6V?

        => We check INTZ at PVDD = 5 & 6.5V, and INTZ remains high 3V3 state. Besides, we also check set up pin as table1.

    Table1

    PVDD            | 5V        | 6V5

    Driver output | Normal | Abnormal

    ------------------------------------------------

    Enable           | 3V3      | 3V3

    Standby         | 0V        | 0V

    INTZ              | 3V3      | 3V3

    FS0, 1, 2        | 0V        | 0V 

    IN+, IN-          | PWM    | PWM

    -----------------------------------------------

    2. If you decrease PVDD back down to 5V, does it go back to normal operation?

       => Yes, as PVDD 5~6V        => Driver normal output

                         PVDD 6.xx~18V => Driver abnormal output

    3. If the load is removed does the abnormal output still occur?

       => Test condition: No load.

    4. BTW, we connect FS0, FS1, FS2, STD pins with pull down R10k to Gnd.

        Do you have recommended pull down R value refer original EVM design(connect to GPIO of MCU MPS430)? 

  • PVDD = 5V, INTZ = 3V3

    PVDD = 6V5, INTZ = 3V3

  • Hello, 

    4. BTW, we connect FS0, FS1, FS2, STD pins with pull down R10k to Gnd.

        Do you have recommended pull down R value refer original EVM design(connect to GPIO of MCU MPS430)? 

    I believe 10k is okay here. 

    Are you measuring the output of the RC filter? Can you instead measure the outputs of the Class-D (should be switching at 400kHz)? I am wondering if this is an issue with the measurement filter.

    Regards,
    Sydney Northcutt 

  • Hi Sydney

    We measured both out( with and without filter)

    waveform are almost the same.


    Behavior of PVDD=5V and 6V5 are the same as above figure.

    Besides, PVDD=6V5 waveform looks like driver active some mode and does not explain on spec. Waveform are regular.

    Could you help to check what mode could active the abnormal waveform as PVDD=6V5?

    Thank you

    Sincerely

    Jax

  • Hi Jax,

    The ouput waveforms with and without the filter should not be the same. I don't believe there should be any mode switch either. 

    Without the filter, there should be 400kHz switching. With the filter, the high frequency component is filtered out and you would see the signal similar to that of your input. 

    Can you probe both in+ and in- with out+ and out- here?

    Regards,
    Sydney Northcutt 

  • Hi Sydney 

    Can you probe both in+ and in- with out+ and out- here?

    1. Could you provide the in+ and in- with out+ and out- Test Point?

        For example:

        Measure IN+            => TP: IN+ to Gnd

        Measure IN+ & IN-   => TP: IN+ to IN-

     

    2. We find DAC signal will pull up by solenoid drive as PVDD > 6V3

    => Why IN+ & IN- will pull up 0V4 as  PVDD > 6V5 and remain 0V4 from 6V5~18V?

     

    Condition:

    We jump IN+, IN- filter circuit with 0ohm as below

    We play DAC1 PWM to Driver and DAC2 keep 0V

    PVDD = 5V Both DAC signal to Driver are fine(TP: DAC1 to Gnd, DAC2 to Gnd)

    As PVDD > 6V3 Both DAC signal to Driver are pull up(TP: DAC1 to Gnd, DAC2 to Gnd)

    (TP DAC1 to DAC2)

    Cause the error PA result.

  • Hi Jax,

    Let me check with design on the pull up portion. 

    I'm thinking this may be an undervoltage issue. The undervoltage protecition does not trigger the INTZ pin and self clears. I believe the output pulsing at the same frequency as the input is due to this protections self clearing functionality as the fault clears but is triggered again the next time the signal is high. 

    Can you probe PVDD while observing the error? You could also try using an external power supply and seeing if the issue is still present. 

    Regards,
    Sydney Northcutt 

  • Hi Sydney 

    Figure could be shown as below. 

    PVDD = 5V, with INTZ, DAC+,  Driver Vout+ to Gnd

     

    PVDD = 7V5, with INTZ, DAC+,  Driver Vout+ to Gnd

    Sincerely

    Jax Lin

  • Hi Jax,

    Thank you for trying these tests. Let me try some things on my end as well.

    Do you have a load you can try with? I'm curious to see if the response will be the same. 

    Also, can you provide your layout for a quick review? 

    Regards,
    Sydney Northcutt

  • Hi Sydney 

    1. Sydney:Do you have a load you can try with? I'm curious to see if the response will be the same. 

        => Jax:No load

    2. Sydney:Also, can you provide your layout for a quick review? 

        => Jax:Figure as below. Thank you

    3. Jax: WE find DAC will be effected @ PVDD >= 6V5.

                  And this situation will not happen on TI EVM board. If input = 0V, EVM output will keep 0V@PVDD5~18V.

    Our condition

        a. Turn off DAC+ and DAC-  and Turn PVDD = 5V, => As expected, Driver I/O equal to 0V

        b. As PVDD > 6V5, DAC+, DAC-, Vout+ and Vout- will change to following waveform immediately. DAC+ and DAC- could not keep 0V.

    L1

    L2(Gnd)

    L3

    L4

  • Hi,

    Thank you for the layout. I’ll be able to give these a review when I return to office next week. 

    Are you seeing the abnormal behavior at PVDD > 6.5 V on the EVM as well? Or is this only observed on your PCB design? 

    If you supply the input signal externally on your board is the issue still present? Since you are seeing differences on your board and the EVM here I believe this will be a good next test.

    Regards,
    Sydney Northcutt