DRV8912-Q1: When outputting a high impedance state, there is still a path between the output and ground

Jacob

Part Number: DRV8912-Q1
Other Parts Discussed in Thread: DRV8816

Tool/software:

Hi, team

I used DRV8912 as a 24V driver, but when the output is disabled, there seems to still be a path between the output pin and ground. Because when there was no load connected, I measured 23.85V with a multimeter between the output and 24V. I'm sure there's no problem with the driver, because when the load is connected, the high impedance state can be pulled to 24V or ground. So why did such a result occur?

Thank you and best regard

6 months ago

0 Joshua Horlander Cruz 6 months ago

TI__Mastermind 26960 points

Hi Jacob,

Can I know the reason for this measurement? The reason that I ask is that if the intent is to determine if the device is in the Hi-Z state, we typically use two 10k ohms resistors, one resistor in parallel with each FET and recommend measuring across these resistors to determine if the half-bridge is in the Hi-Z state. With this resistor divider you should see half the voltage at the OUTx pin since the device is Hi-Z. Without the resistors the OUTx node will be fully floating which would make it so that the probe GND would pull OUTx to whatever its reference voltage is. which is leading to the reading you saw.

Regards,

Joshua

0 Jacob 6 months ago in reply to Joshua Horlander Cruz

Prodigy 40 points

Hi Joshua，

I conducted an experiment using your method and found that the voltage to ground is 11.95V and the voltage to the power supply is 12.22V. It seems that there is indeed some paths inside the device can conduct current, like a pull-down resistor of about 500K inside the chip? (This suspicion arises because I previously observed a similar phenomenon when working with the DRV8816. There is also relevant explanation in the forum.DRV8816: disabled DRV8816 is not 'Z' at output! - Motor drivers forum - Motor drivers - TI E2E support forums) I would like to know if DRV8912 is also like this, or if there are any other reasons? I would greatly appreciate it if you could help me explain this phenomenon. In addition, it should be noted that open circuit detection is not used in the scheme.

Thanks.

0 Joshua Horlander Cruz 6 months ago in reply to Jacob

TI__Mastermind 26960 points

Hi Jacob,

I will reach out to my team about this to see where the difference in voltage is coming from. I will aim to update you by next Tuesday.

Regards,

Joshua

0 Jacob 5 months ago in reply to Joshua Horlander Cruz

Prodigy 40 points

Hi Joshua，

OK, received. Thanks for following up, looking forward to your update.

Regards,

Jacob

0 Joshua Horlander Cruz 5 months ago in reply to Jacob

TI__Mastermind 26960 points

Hi Jacob,

I am still waiting for a response from our design team. I will aim to provide you with an update by Thursday.

Regards,

Joshua

0 Jacob 5 months ago in reply to Joshua Horlander Cruz

Prodigy 40 points

Hi Joshua,

Just a quick follow-up: Have you heard back from the design team yet?

Thanks!

Jacob

0 Joshua Horlander Cruz 5 months ago in reply to Jacob

TI__Mastermind 26960 points

Hi Jacob,

I have not heard back from our design team yet. I will push to get a response by EoD tomorrow.

Regards,

Joshua

+1 Joshua Horlander Cruz 5 months ago in reply to Joshua Horlander Cruz

TI__Mastermind 26960 points

Hi Jacob,

There is an resistor to GND on the high side gate which is causing the internal leakage path. The path of source to gate is though a Zener protection diode from the high-side FETs gate to source nodes.

Regards,

Joshua

0 Jacob 5 months ago in reply to Joshua Horlander Cruz

Prodigy 40 points

Hi Joshua,

Thank you for your comprehensive response — it has fully resolved my inquiry regarding the design specifications.

Your support is highly valued. Thanks!

Jacob