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DRV2511-Q1: Power Rail Noise Correlated with Driver PWM Output

Scott Barnette
Prodigy 10 points
Part Number: DRV2511-Q1


Tool/software:

Noise is present on the PVDD/AVDD Vbatt supply rail, as well as on VCC1—the 3.3V regulator output from the CAN SBC, which is tied to the INTZ pull-up resistor. One chart illustrates Vbatt (orange trace), connected to PVDD/AVDD, alongside the 3.3V VCC1 rail (blue trace). The second chart shows the PWM output from the driver chip (blue trace) in comparison with the 3.3V VCC1 regulator output.

The noise appears to correlate with PWM switching activity from the driver chip that drives the voice coil. It occurs only when EN is high, even with no voice coil load connected. When EN is low and PWM activity is still present, the noise does not appear on the power rails.

To rule out the SBC’s 3.3V regulator as the source of the issue, I patched in a 3.3VDC supply from a desktop PC power supply—but the issue persisted.

  • 0
    TI__Genius 11152 points

    Hi,

    The schematic looks correct.. What is generating the VCC1 supply?

    In that last image, is the Vreg the REG pin (6, 7) of DRV2511-Q1? This is quite a bit of noise for the gate drive supply..

    Is IN+ pin pulled down to GND with a 3.3kOhm resistor? You should capacitively couple this pin to GND for single PWM input. It has an internal bias. 

  • 0 in reply to Kelly Griffin
    Prodigy 10 points

    Vcc1 is generated by PIN 13 of the CAN SBC...... MFR PN: TLE9461ESV33XUMA1
    Last image, yes I believe the software engineer was probing Vreg Pins 6 & 7
    Yes, both IN+ (R18) and IN- (R21) are populated present in the circuit as the eval board and typical application schematic.  

    To note:
    -For IN+ and IN- we don't have the RC filters populated, the 3.3k resistors (R16, R17, R19, R20) are shorted.  
    - We are trying to implement the differential input application driving one single voicecoil.  In our design we have two drv2511-q1 ICs, with each having 1 dedicated voicecoil.  

  • 0 in reply to Scott Barnette
    TI__Genius 11152 points

    Hi Scott,

    I missed your note on the 3.3VDC supply, so no issue with VCC1.

    That 2nd graph image shows Vreg = ~0V with noise (or is this VCC1 being AC coupled?). It is strange to see noise with just the PWM signal being active.

    The REG pin should be stable after the part starts up - the first few switches on the output may have a little noise on them as the REG is supplying the Gate drive of the output FETs. Once the bootstrap caps charge, there should be very little noise here.

    One thing to note is that REG is supplied from AVDD/PVDD. So even with decent PSRR on the internal LDO, you may see some noise coupling from AVDD to REG. 

    It is difficult to know what is causing this noise. Let me reach out and see if we can more easily solve this over email.