DRV8305-Q1: Input current too high after setting EN_GATE

Hi John,

Although the schematic is a little unclear, it looks like VCPH to PVDD cap is 4.7uF with a 35V rating?

In the previous E2E it was mentioned that the rating should be PVDD x 2. It could be that your capacitor is being de-rated?

can 0603 caps fit on your board for CP1 and CP2? This would be a good test to do is seeing the behavior on the same board with the different sized capacitors.

Regards,

Yara

Hello Yara,

Thank you for your fast response. Sorry for the low resolution of the schematic. If you need, please let me know how I can send you the schematic in a higher resolution.

The VCPH to PVDD cap used is a takeover part from the board where the DRV8305-q1 is working as expected. From the previous E2E, I understand that CP1 should be rated for PVDD and CP2 should be rated for PVDD x2. Both of the caps CP1 and CP2 are rated for 50 V.

In the previous E2E, I have not seen a rating for the cap VCPH to PVDD x 2. The datasheet for the DRV8305 SLVSD12D is showing 2,2 μF rated for 16 V for the VCPH to PVDD cap:

Please confirm PVDD x2 for VCPH to PVDD cap.

Good idea to try the 0603 size for CP1 and CP2. I soldered in the 0603 caps yesterday, but unfortunately no improvement. :-(

I have checked the values of these parts and measured in circuit with an LCR meter to confirm. Everything seems to fit.

On this version of the board, I have also closely followed the layout guidelines in section 10.1 of the datasheet.
So in this version:

• the DVDD and AVDD 1 μF caps are connected directly to the adjacent GND pins of the DRV8305-Q1
• CP! and CP2 are placed dorectöy mest tp tje DRV8305-Q1 charge pump pins
• The VCPH 2.2-μF and VCP_LSD 1-μF bypass capacitors are placed close to their corresponding pins
  with a direct path back to the DRV8305-Q1 PVDD for VCPH and GND for VCP_LSD
• The PVDD 4.7-μF bypass capacitor is placed as close as possible to the DRV8305-Q1 PVDD supply
  pin
• footprint was updated to the version in the datasheet Revision D
• The loop length for the high-side and low-side gate drivers have been minimized
• The VDRAIN pin is routed through a 100-Ω series resistor directly to the MOSFET DRAIN

Here is a picture of the layout:

I have checked everything again and again and have not found the mistake. Could it be in the new foot print?

Kind Regards,

John

Hi John,

Sorry for that mistake you are correct the VCPH to PVDD cap is okay to be rated for 16V, so the 35V rating you have is good

I'm not sure what sort of affect having 4.7uF instead of 2.2uF would have though, this I can look into a bit further.

Your caps do look pretty close to the device so I don't think it is a concern they are too far away. I'm not sure I entirely understand what the the differences are between your current layout and your previous one. Are you able to have a side by side comparison of the changes you made?

Regards,

Yara

Hello Yara,

Thank you for the confirmation.

The 4.7 µF is also on the prototype that is working, so I have not pinned this as the issue, but I will test.

As suggested, I have made a comparison of the layouts, but I do not see a potential cause. What do you see?

The layout on the left is ok, while the layout on the right draws 175 mA more
current with the same GDU setting when the EN_GATE is set.

I have checked the sizes of all the external components and they are the same.
It is still unclear where the extra current draw is coming from. The voltages
on all the pins are the same, and the signals on CP1 and CP2 are similiar.

I am really at a loss here, where the problem could be.

Kind Regards,

John

Hello Yara,

Do you have any new inputs on this issue?

Further prototypes have been stopped until this issue is solved,

so at the moment this is the job stopper.

Kinds Regards,

John

Hi John,

Apologies for the delay. The "not okay" layout in this screenshot doesn't look like it would be the reason behind the excess current draw (it's pretty similar to what is in the datasheet) I'm assuming there is a GND pour the thermal is connecting to on a different layer? One thing that is just a little concerning and I'm not sure if its related to this issue but the clearance between the thermal pad and the pins is pretty small, it doesn't look this close on the "okay" layout?

Have you probed VCPH to PVDD and VCP_LSD to GND on a scope right after ENABLE is pulled high? are you able to provide these waveforms? essentially I'd be looking for any kind of unstable behavior when the device is enable

Same note for CPH and CPL (1 & 2), it would be good to see waveforms of these two signals

Something you can do as well to isolate where the issue could be stemming from is removing the FETs. If the current drops back to 150mA you saw on the previous design then that tells us to focus on GHx and GLx behavior, if removing the FETs doesn't fix the issue then we know we can focus on the charge pump

Regards,

Yara

Hello Yara,

thank you for your suggestions.

Yes, the thermal pad is larger on the version with the problems as in the the Datasheet revision D, to the pad is closer to the pins. However, a part of the pad is covered with solder stop:

I have double checked the dimension to the drawing and they fit.

First pictures of VCPH to PVDD with a diff. probe over the cap and VCP_LSD to GND with a normal probe, triggered on EN_GATE.

Here some screenshots of VCPH, VCP_LSH, CP1H and CP2H to GND.
Please let me know if you need the voltage directly over the caps.

Tomorrow I will make the same measurements on the board revision which is okay
as well as on the BoostXL-DRB8305 for comparison and post them for your reference.
What kinds of things are you looking for here?

The test with removing the MoSFETS I will also do tomorrow. I will probably have
to disable VDS Protection at VDS_MODE, right? Is there any other protection
that needs to be disables?

Kind Regards,

John

Hi John,

Essentially I'm just looking for any abnormal behavior on these power blocks that could explain the reason for the increase in current draw. VCPH and VCP_LSD don't look concerning. It would be nice to see CPH to CPL. I think a comparison between this design and the previous design would be great, if we see any drastic differences then we can take a look at the layout regards PVDD and VM

If you're going to remove the FETs yes I believe you would have to disable VDS protections since it might false trigger (I think SHx might float up causing the false trigger) I think this should be the only fault that needs to be disabled.

Regards,

Yara

Hello Yara,

Thank you for your feedback and suggestions.

So, some screenshots as above, but from the board which is working.
First VCPH to PVDD with a diff. probe over the cap and VCP_LSD to GND with a normal probe, triggered on EN_GATE:

and then VCPH, VCP_LSH, CP1H and CP2H to GND:

When I compare, they seem to be very similar. Maybe you see something?

Since I had gate resistors, I did not solder out the MoSFETs, but rather
the gate resistors. I also disabled all faults and warnings in the DRV8305
and checkted to see that the outputs were indeed switching.

And voilá, the current sunk to from 380 mA power input to the board, to
101 mA. I then soldered in the gate resistors one at a time. When I add
the gate resistor for GH_A, GH_B and GH_C, each connection adds 10 mA
to the input current. GL_A, GL_B and GL_C each add around 64 mA to the input
current which is 54 mA more than the high side or 162 mA altogether.

Nothing has changen either in the GDU register setting nor in the code
in the MCU. I will be out of office tomorrow, so Monday I will look at the
gate signals. With this new information, do you have any suggestions?

Kind Regards,

John

Hi John,

I agree the waveforms look nearly identical and nothing really stands out.

Its great that you added the FETs back a few at a time! We should focus on the low-side FETs, 64mA jump for each FET is pretty significant. My initial thoughts on this would be to observe the state of the GLx pin at the DRV8305 pins, maybe its floating when its supposed to be low?

Were there any layout changes in the power stage in the latest revision?

Are there gate-to-source resistors in place? if so what are the values?

Regards,

Yara

Hello Yara,

Yes, I also noticed that this issue was apparent in the low side MoSFETs. There were not changes
to the layout, but when you say gate-to-source resistor, that rings a bell. They are designed to 100k
which I think should be enougn, but this one I have not checked on the board, to see what our
EMS actually put in. I will check on Monday and share the results. Thank you for the tip!

Kind Regards,

John

No Problem! I'll be waiting for your update.

Hello Yara,

well, it has been an interesting day,. As discussed, I measured the gate-to-source resistors and sure enough,
the planned 100 K had been assembled with 10K. For that, I had a little talk with our EMS.

Nevertheless, this did not improve the situation. Then realised, that I had also moved the gate resistors
closer to the DRV8305 and farther away from the MoSFET. This had dire consequences, because I had
not recalculated the snubber for the change in stray trace inductance. So I removed the snubber resistor 
from low side of phase B and the current dropped 22 mA. I then moved the gate resistor right next to the
Cgs and patched a wire from there to the DRV8305. Current down to the expected 15 mA. So, little change
resulting in a big consequence.

Tomorrow I will recalculate the snubber for the new trace and compare to the value where Rg is very close
to Cgs to see which gives the best performance (i.e. switching ringing and least current consumption) and 
share the results.

For anyone interested, there is a great procedure from TI for calculating a snubber which can be found here:
https://www.ti.com/document-viewer/lit/html/SSZTBC7

So, even though the mistake was not in Rgs, you got me going on the right path. Thanks for that! :-)

Kind Regards,

John

Hello Yara,

Recalculated snubber and moved Rg as close to the gate as possible. Result confirmed. Thanks again for your support

Kind Regards,

John