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DRV8305-Q1EVM: VCPH_OVLO_ABS triggers with a high speed motor

Part Number: DRV8305-Q1EVM
Other Parts Discussed in Thread: DRV8305, DRV3255-Q1, DRV8363-Q1, DRV8363-Q1EVM

Tool/software:

I am running a DRV8305-Q1EVM board with a high speed motor with a 34V power supply. I also use the InstaSPIN_UNIVERSAL software, running Proj_Lab5a.

I am able to tune the motor and create a custom user.h file that is used to compile the .out executable for the GUI.

The motor operates well up to 10,000 rpm and is rated to operate to much higher speed. (Its native controller can operate the motor well above 10,000 rpm.)

When I reduce the commanded setpoint from 10,000 rpm down, the back-emf causes the PVDD and VCPH to float up and exceed their respective thresholds (35V for PVDD and 60V for VCPH).

While the PVDD_OVFL only produces a WARNING, the VCPH overvoltage causes a FAULT and shuts down the board. I can verify this process through the 0x3 D0 register and by monitoring the relevant scope traces.

Question: Is there a way to reduce/remove the unwanted increase in VPDD and VCPH due to the back-EMF?

  • Hey Rostislav,

    Thank you for the question. We will aim to provide feedback early next week.

    Best,

    Akshay

  • Hi Rostislav,

    So, your concern is how can the charging of the PVDD and VCP during motor slow down be prevented?

    Are you trying to fully stop the motor or simply reduce the speed? 

    Also, can you provide waveform of the PVDD and VCP, and NFAULT at time of fault?

    Please let me know if my understanding is correct.

    Thanks,

    Joseph

  • Joseph, 

    yes, your understanding is correct - I am trying to slowdown the motor.

    Don't have the traces handy - will work on getting them later.

  • Hi Rostislav,

    Thanks for the clarification. Most likely I will need to see waveforms to form a meaningful opinion.

    Here are some other questions in the meantime:

    1. Maybe you are trying to reduce the speed in too big of a step? Is there a deceleration parameter anywhere which is at play here?

    2. You mention that it works up to 10000 rpm just fine, meaning that it is able to operate at the reduced speed, at least for a little bit, during the start up /ramp up to 10000 rpm? What is the exact value for the new target?

    Thanks,

    Joseph

  • Joseph, Uploading a couple of images to explain my issue. In both images: Channel 1 (yellow) is the Mot_A signal to one of the motor coils, Channel 2 ( blue) is the nFAULT signal, Channel 3 (red) is PVDD, Channel 4 (green) is VCP. The first image shows the initiation of the slow down signal from 10,000 rpm at 200 rpm/s. The nFAULT is first triggered by PVDD going over 35 volts and looks like is pulsed for the first ~800ms, as intended for that WARNING. Over the next 800 ms (see the second image that shows a longer time frame) the PVDD and VCP rise and eventually the VCP exceeds 60 volts, which shuts down the output and pegs the nFAULT to 0.

  • Hi Rostislav,

    Thanks for the waveforms. I can see the behavior you describe. At least the device's protections are working properly!

    To me, this behavior seems counter intuitive as I would expect motor current to decrease with a lower target RPM... Have you probed the inputs and gate signals during this condition to see if they match what you expect from the code? (E.g. lower duty cycle on input pwm)

    Thanks,

    Joseph

  • Hi Joseph, 

    Yes, I am definitely glad that the protection is working - haven't fried the board, yet!

    I believe the reason for the PVDD and VCP voltage increase is due to the back-EMF coming from the motor. Specifically, I think the issue may be "VM pumping". If I command the reduction in speed at a slower rate, for example 50 rpm/s instead of 200 rpm/s, I don't see the voltage PVDD or VCP go up at all. The issue is that I want to slow down at 200 rpm/s and faster and don't know how to address the problem within the DRV8305-Q1EVM hardware architecture - I think I may need to implement a software solution, but not sure what exactly I need to do.

    As far as the Gate signals, I am attaching two images, where the red channel is now GHA voltage. The GHA voltage seems to behave as expected. I am not sure that is a problem. 

  • Joseph,

    Also, a few related questions... The DRV8305 Datasheet states 4.4-V to 45-V operating voltage range. However, the PVDD_OVFL is triggered at 35-V. That seems a bit inconsistent. Could you please clarify? I'd really like to run the EVM board at 45 V, if I can.

    If that is not possible, are there other automotive quality EVM boards that are capable of going to 45V or 48V operation? I see DRV3255-Q1 on the TI website, but for some reason the Datasheet and EVM are restricted. I work for a US company, so hopefully, I can get access to that info. Thanks!

  • Hi Rostislav,

    Thanks for the extra info. I agree that this is the issue is VM pumping now that we see the gate behaving as expected.

    Now we have few options to prevent this issue.

    The easiest and most reliable solution will be to use a TVS diode as mentioned in the VM Pumping FAQ you linked. I understand this would add extra cost to the system but it would be a simple way to resolve the issue. If you would like to pursue this solution I can provide additional advice later.

    Software solution may be possible, but this approach would be much more difficult and I could see potential problems arising.

    As for your second question, yes, this is because the operating voltage meant for this device is 24V.

    As a rule of thumb, we spec the abs max voltage of the device at around 2X the desired operating voltage to provide very safe/high abs max values for the target voltage rail, which is why you see a 45V abs max for the device, but protections kicking in at 35V.

    If you would like to operate at 48V, I can recommend the DRV8363-Q1, which is one our our latest and greatest devices that also has the ASIL-B automotive rating. EVMs should also be available for this device. However, the EVM operates with sensored trapezoidal commutation out of the box and you would have to write your own software to pursue FOC commutation.

    Thanks,

    Joseph

  • Thanks Joseph,

    I would like to pursue the TVS option as a short-term solution. Would be great to get a simple schematic and parts for that solution. Also, do you think a simple Zener with a resistor between the power supply terminals may work, as well? 

    I did review DRV8363-Q1 and it looks appealing. However, I do need to make it work with FOC. Do you think it may be straightforward to implement the software FOC option with minor modifications if I combine the DRV8363-Q1EVM with LUNCHXL-F28027F and use the software provided for DRV8305-Q1EVM, since that board uses F28027F MCU? I suspect that I may have to adjust the GPIOs, but otherwise the software may work. Any thoughts?

    Thanks and really appreciate your help!

  • Hi Rostislav,

    No problem, happy to help out. 

    I'm not too confident in determining whether the zener or TVS would be a better choice here... I think it's worth it to make a modification to the board to try out each of them to observe the behavior empirically. 

    The general placement I would suggest would be seen here in the diagram at TS2 found in the FAQ. from VM node near device to PGND.

    The important thing in the selection of the diode whether it be TVS or Zener is the breakdown voltage, and the power rating. You want to select a breakdown voltage such that it triggers:

    1. Not during normal operation, (so a little bit above highest nominal operating voltage)

    2. But also, low enough to breakdown and drain the excess charge before protection circuitry kicks in

    3. Another consideration is making sure the diode is rated to handle the amount of power that would be flowing through it during the breakdown operation.

    As for the FOC compatibility regarding the DRV8363-Q1EVM I can say that I have seen customers use alternate board's software with non-compatible EVMs. You would have to blue-wire over the corresponding GPIO-s correctly as you mentioned, since they will not mate correctly with the header's pinouts. I have seen this done before but my help will be very limited in this scenario.

    I'm also not sure how SPI configuration would work in this case since the SPI frames are different between devices, these functions would likely have to be rewritten entirely.

    Thanks,

    Joseph