Part Number: DRV8353RS-EVM
Hi
I am using the DRV8353RS with an STM32F407VGTX in 1xPWM synchronous mode. The MCU drives INHA (PWM), INLA, INHB, INLB, INHC and INLC, and I am trying to verify the gate‑drive outputs on the DRV8353RS‑EVM using an LA1010 logic analyzer.
For debugging I command only the ALIGN state every 10 ms from the STM32 (no stepping yet). According to Table 3 in the datasheet, for INHC = 0 my logic inputs during ALIGN are:
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INHA: 20 kHz PWM (about 50% duty)
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INLA = 1
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INHB = 1
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INLB = 1
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INHC = 0
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INLC = 1 (no brake)
I probe the following EVM test points with the logic analyzer:
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GHA, GLA, GHB, GLB, GHC, GLC
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INHA, INLA, INHB, INLB, INHC, INLC
However, the gate‑drive outputs I measure on GHA/GLA/GHB/GLB/GHC/GLC do not match the expected pattern from Table 3 for the ALIGN state.
B.R
Ashish
