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DRV8162: DRV8162LDGSR Design Queries

Prachi Moghe
Prodigy 171 points

Part Number: DRV8162
Other Parts Discussed in Thread: CSD18543Q3A,

Hi,

Referring to DRV8162LDGSR specifications, please see below queries.

As per design requirements, the Input is 5V 1.2KHz PWM, the only signal to drive HS & LS, and no other GPIO is available to clear the latched condition during fault. 

  1. Can this device be used to drive high-side load? 
  2. Does it use same VDS threshold for both HS and LS FETs with the resistor connected to VDSLVL pin? In case, different MOSFETs are used for HS & LS, which one shall be considered critical for OCP VDS monitoring?
  3. Using IDRIVE1 and IDRIVE2 pins resistor, same gate drive current applicable for both HS & LS MOSFET?
  4. How is the slew rate managed?
  5. If nDRVOFF pin is tied to 5V supply, will it impact on its operation?
  6. Can GVDD and GVDD_LS be tied together to 5V? WIll it work with 5V(+/-2%) which will be an LDO output in our application, since the operating min is 5V for GVDD, GVDD_LS? 
  7. Kindly guide us on the latch reset strategy.
  8. In case INL/EN is tied to 5V in 1-pin PWM mode, how will the fault-clearing mechanism work? Latched fault recovery INH(IN) = Low & INL(EN) = Low for > tCLRFLT (Reference- Table 7-7)

Regards,

Prachi

  • 0
    TI__Mastermind 26481 points

    Hey Prachi,

    1. Yes, See figure 7-3.
    2. Yes same VDS LVL for HS and LS is used. The low-side VDS monitor of DRV816x is not available if independent PWM mode is configured.
    3. Yes, Same Idirve for HS and LS is applied. based on the tbale 7-4 in DS
    4. Slew rate is adjusted based on the Idirve setting chosen (Trise/fall = QGD/ Isource/sink)
    5. nDrvoff being tied to %v means you cant use the gate driver shutdown using nDRVOFF pin. If this is not needed then no problem.
    6. The GVDD UV threshold determines if the device will throw a UV fault.  So if the GVDD is above this value then it should not be an issue. Also I assume 5V gvdd is enough to fully enhance the MOSFET being used in your application.
    7. You can recover a latched fault for VDS by  INH(IN) = Low & INL(EN) = Low for > tCLRFLT
    8. I recommend connecting INH, INL to an MCU GPIO to clear fault. or if using independent loads, disabling VDS OCP.

    Best,
    Akshay

  • 0 in reply to Akshay Rajeev Menon
    Prodigy 171 points

    Hi Akshay, 

    Thank you for your feedback.

    Figure 7-3 shows Independent PWM mode with load connected between HS and LS. Our application needs the inductive load to be connected between Half-bridge terminal (SH) and the battery (Vbatt or VDRAIN) as shown in below figure, controlling both HS and LS FETs through a single PWM input, and current recirculation with HS FET. Please check below configuration.

    • INH/IN to 1.2kHz PWM

    • INL/EN to 5V

    • 1-pin PWM mode

    • Load (120mH or 10mH) as shown below with load current 6A

    • Duty cycle: 0, 5%-95%, 100%

    Please confirm if this configuration is valid with all integrated protections, mainly OCP through VDS monitoring available. 

    To recover the latched condition, we do not have two separate signals from the MCU for INH and INL. As I mentioned earlier, there is only 1.2kHz PWM input which can be connected to INH; INL/EN to be tied to 5V configuring it as 1-pin PWM mode.

    So, please guide us on how we can recover the latched condition here. Will driving the INH/IN pin low with 50% DC (~400us) alone help to reset the latch?

    Or do you recommend 2-pin PWM mode with INH & INL synched such that only High and Low states of the load are achieved, disabling Hi-Z state

    Also, do you recommend external diodes across HS and LS FETs for current recirculation in our application? 

    Regards,

    Prachi

  • 0 in reply to Prachi Moghe
    TI__Mastermind 26481 points

    Hey Prachi,

    What is the load in this application?

    Got it. If VDS ocp is triggered and you are unable to pull, INH and INL low then you will not be able to clear the fault. 
    50%DC is not below the logic low threshold.

    Prachi Moghe said:
    Or do you recommend 2-pin PWM mode with INH & INL synched such that only High and Low states of the load are achieved, disabling Hi-Z state

    Could you explain  a bit more on how this would be achieved? and how VDS OCP can be cleared?

    Prachi Moghe said:
    Also, do you recommend external diodes across HS and LS FETs for current recirculation in our application? 

    What is the load in this application?

    Best,

    Akshay

  • 0 in reply to Akshay Rajeev Menon
    Prodigy 171 points

    Hi Akshay,

    The load is 10mH or 120mH, with 6A rms current.

    We are exploring if we can make use of DRV8162L feature of flexible PWM control in our application with single 1.2kHz PWM input. If you have any feedback on the same, please share. 

    Will this device operate during cold cranking condition, where battery voltage can go down to 3.2V?

    Since the gate voltage (GVDD_LS) is 5V, is it okay to use power MOS for LS or do we need to consider the logic FET? In case, different FETs with unequal RDSon are used for HS & LS, which one shall be considered critical for OCP VDS monitoring in 1-pin or 2-pin PWM control?

    Thanks.

    Prachi

  • 0 in reply to Prachi Moghe
    TI__Mastermind 26481 points

    Hey Prachi,

    How are you going to sync the single PWM in the 2x mdoe? IF you use an inverter to flip the INHx then will you be able to turn the reference to the inverter off when you need to clear the fault?
    What MCU is being used in your application?

    Also with 5V GVDD, you need to ensure that the FET can be sufficiently enhanced with that voltage. If you would like can you share the mosfet DS?

    Best,

    Akshay

  • 0 in reply to Akshay Rajeev Menon
    Prodigy 171 points

    Hi Akshay,

    We don't have the MCU on board; the PWM is generated externally to drive the load. 

    MOSFET for reference- CSD18543Q3A

    Kindly address pending questions-

    • In case, different FETs with unequal RDSon are used for HS & LS, which one shall be considered critical for OCP VDS monitoring?

    • Which Flexible PWM mode (1-pin or 2-pin) do you recommend for our application)? 

    • Will this device operate during cold cranking condition, where battery voltage can go down to 3.2V?

    • Do you recommend external diodes across HS and LS FETs for current recirculation in our application?

    • Recommendation to reset the latched device where only 1.2kHz PWM is available

    Additionally, can you please share PSpice simulation model for DRV8162/ DRV8162L?

    Regards,

    Prachi

  • 0 in reply to Prachi Moghe
    TI__Mastermind 26481 points

    Hey Prachi,

    The FET you have linked will not be sufficiently enhanced with a 5V GVDD so the RDS on will be higher.

    For VDS, the first one to trigger will be the one that exceeds the VDSLVL threshold (assuming that gate is the one switching).

    So higher rdson will trigger sooner (V = I*R).

    In order to rest a VDS fault (unless VDS fsault is disabled) you will need to pull INH and INL low or do a GVDD power cycle.

    In 1x mode if you use an inverter to flip the INHx then will you be able to turn the reference to the inverter off when you need to clear the fault?

    Prachi Moghe said:

    Will this device operate during cold cranking condition, where battery voltage can go down to 3.2V?

    • Do you recommend external diodes across HS and LS FETs for current recirculation in our application?

    Let me check with the team on this.

    We do not have a Pspice simulation model for this driver.

    Best,

    Akshay

  • 0 in reply to Akshay Rajeev Menon
    TI__Mastermind 26481 points

    Hey Prachi,

    The device was not intended for such low Drain voltage operation, so the Trickle charge pump will not be working at 3.2V.

    As for the external diodes, I dont think they are needed from what I see. I would like to understand why a didoe between drain and SHx cant be used instead of the HS FET in this application.

    Best,
    Akshay