DRV8300: DRV8300 + STP15810: Maximum Number of Parallel MOSFETs per Phase

Thumula Bhargav

Part Number: DRV8300

Hii TI Team,

I am using the DRV8300 gate driver along with STP15810 MOSFETs in my motor control design.

I would like to understand how many MOSFETs can be connected in parallel per phase when using the DRV8300.

Are there any limitations or design considerations related to gate drive current, switching speed, PCB layout, or thermal performance that determine the maximum number of parallel MOSFETs?

can i have any furture clarification for this mosfet i am going to use in this following :
• STP100N10F7 — 100 V, 80 A (TO-220)
• STB100N10F7 / STD100N10F7 — 100 V, 80 A (D2PAK / DPAK)
• STP240N10F7 — 100 V, 110 A (TO-220)
• STP120NF10 / STW120NF10 — 100 V, 110 A (TO-220 / TO-247)

Any guidance or reference designs would be very helpful.

Regards,

Thumula Bhargav

2 months ago

0 Akshay Rajeev Menon 2 months ago

TI__Mastermind 26481 points

Hey Thumula,

I recommend checking out this app note on driving parallel FETs: https://www.ti.com/lit/ab/slvaf39a/slvaf39a.pdf

Many of the ideas can be applied to your case. major question is the gate current (1/2A source/sink) being split between multiple MOSFETs.

We have a general layout guide which is still applicable, mainly ensuring that each half-bridge is similarly positioned to the others so that one phase isnt worse in terms of parasitics.

[FAQ]: Motor Driver Layout Best Practices

Let me know if you have any other questions.

Best,

Akshay

0 Thumula Bhargav 2 months ago in reply to Akshay Rajeev Menon

Prodigy 40 points

Hello Akshay

Aually we are trying to go with DRV8300 with our process being in so we request you the information that how many mosfet's can able to connect in parallel using DRV8300 itself

Thank you for your support and information

Regards,

Thumula Bhargav

0 Akshay Rajeev Menon 2 months ago in reply to Thumula Bhargav

TI__Mastermind 26481 points

Hey Thumula,

You can use the gate current and the QGD of the MOSFET to see how many MOSFETs you can parallel before being unable to turn them on in the desired slew time.

T(rise/fall) = Qgd / I(source/sink) --> 1/2A limit in DRV8300

Increase Qgd based on number of FETs in parallel.

Trise/fall is the desired VDS slew time (typically 200ns rise time)

Note: the gate resistor you choose will further limit the gate current

Best,
Akshay

0 Thumula Bhargav 2 months ago in reply to Akshay Rajeev Menon

Prodigy 40 points

Hello Akshay,

Thanks for the formula.

For our MOSFET, Qgd ≈ 13 nC. Using DRV8300 (~0.5A gate current) and ~200ns desired rise time gives ~100nC total, which theoretically allows ~7 devices. After practical derating, this suggests 3 MOSFETs safely in parallel, with 4 as an upper limit under optimized layout and low gate resistance.

Please confirm if 3 parallel FETs per switch would be a reasonable design target with DRV8300.

Regards,
Thumula Bhargav

0 Akshay Rajeev Menon 2 months ago in reply to Thumula Bhargav

TI__Mastermind 26481 points

Hey Thumula,

This should be reasonable.

best,
Akshay

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DRV8300: DRV8300 + STP15810: Maximum Number of Parallel MOSFETs per Phase