DRV8300DIPW-EVM: DRV8300 Parallel MOSFET Layout – Gerber Review Guidance

Hi Thumula, 

I think the easiest method would be to review key checkpoints / screenshots of specific areas of concern on the layout. 

I'm glad you are aware of important considerations when using parallel MOSFET designs. What you mentioned will all be good to look at.

To start, we can look at:

1. Power loop / current return path to driver

2. Length and width of gate traces / impedance matches between paralleled gate traces

3. Variation in distance between fets of the same phase

4. Variation in distance between fets of each 3 phases

5. Specs of the MOSFETs used (Qgtotal, Qgd, etc)

Thanks,

Joseph

Hi Joseph,

Thank you for the clarification and for outlining the key checkpoints to focus on.

As suggested, I will share layout screenshots of the specific areas for review, including:

1. Power loop and current return path from the DRV8300 to the MOSFETs

2. Gate drive routing for the paralleled MOSFETs (trace length, width, and symmetry)

   • Maximum gate trace length: 70 mm

   • Gate trace width: 30 mils

     3. MOSFET selection details (Qg, Qgd, total gate charge, etc.

For reference, the MOSFET used in this design is STP100N10F7, with three devices paralleled per switch.

I will upload the screenshots highlighting these regions shortly so we can review them step by step.

Appreciate your guidance on this—our goal is to validate the gate drive balance, power loop parasitics, and thermal symmetry before fabrication to avoid any switching imbalance or overstress.

Best regards,
Thumula Bhargav

Hi Thumula,

Thanks for the extra information and initial screenshots. The trace width and via stitching looks good.

Let me know if you have more specific areas you would like to review.

Thanks,

Joseph

Hi Joseph,

Thank you for the feedback on the trace width and via stitching — glad to know that part looks good.

I would like to get your guidance on a few additional points regarding our power stage design.

Our board is designed for 4 kW continuous power, operating at 64 V and up to 60 A.

1. Power Loop / High Current Path
   We are evaluating the high-current path implementation. For the top layer copper area, we are considering:

   • Additional copper reinforcement using copper bars, or

   • 3 mm lead-coated copper, or

   • Thick copper with direct heatsink mounting. 

   Between the MOSFET , we plan to use a thermal pad for isolation and heat transfer.
   From a layout and reliability perspective, would you recommend any specific approach for minimizing parasitics and improving thermal performance at this power level?

2. MOSFET Gate Charge and Parallel Configuration
   We are using STP100N10F7 with:

   • Qg (Total gate charge) = 61 nC (typ) at VDD = 50 V, ID = 80 A

   With this we are planning three MOSFETs in parallel per switch, do you see any concern from a gate drive capability standpoint with DRV8300, or does this configuration look acceptable?

3. Gate Routing Topology
   In the shared layout image, the yellow traces represent the gate routing, which are symmetrically branched from the driver to each parallel MOSFET.
   Could you please confirm if this routing style is appropriate for balanced switching, or if you would recommend any modification?

4. Schematic Review
   I will also upload our schematic for the power stage and gate drive section. If possible, could you please review it and let us know if there are any concerns or recommended improvements?

Our goal is to ensure proper current sharing, stable switching behavior, and reliable thermal performance before moving to fabrication.

Looking forward to your suggestions.

Best regards,
Thumula Bhargav


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Hi Thumula,

Thank you for the extra information. Much appreciated.

Here are some of my thoughts regarding paralleling.

1. I see that you are using 64V operating voltage. This should be ok, as long as the SHx node does not exceed 85V as outlined in the datsheet absolute max table. I know this is difficult to predict from just a design phase, but I would monitor the voltage seen on SHx carefully once hardware is in hand. Spikes on this node exceeding the abs max are possible sources of driver damage.

2. I feel like a heatsink would be a good move here if possible. Managing thermals are important in parallel operation operation. Again, in this system I know it is hard to predict without having the hardware, but a heatsink would definitely help thermal performance, and would likely help to preserve lifetime reliability of the system.

3. Have you included gate resistors, (or at least 0 ohm resistors so these can be added if needed)? The driver's current should have no problem driving 3 61nC fets. My worry is the other way around, will it be too much gate current? In this case, you would need to plan to have gate resistance in order to make sure the drive current is finely tuned for your system. You can modify the resistance values during testing to find an optimal value. Making sure the gates are not driven too hard will do you much good in reducing potential ringing/spiking issues on SHx. 

Let me know if there is anything else I can help with.

Thanks,

Joseph

Hi Joseph,

Thank you for your detailed feedback and technical insights. I truly appreciate your time reviewing the design and providing valuable recommendations regarding paralleling operation.

Based on your comments, I would like to share a complete schematic-level clarification and review summary of our design for your further inputs.

If there are any additional schematic-level improvements you recommend for robustness, EMI control, or long-term reliability, please let me know.

Thank you again for your detailed review and support.

Best regards,
Thumula Bhargav

Hi Thumula,

No problem, I'm glad I could help out.

Please attach the PDF of your schematic here and I can review.

Thanks,

Joseph

Hi Joseph,

Thank you again for your support.

Schematic Review
I am resharing the schematic link here for your convenience. I had previously shared it in this forum thread, but attaching it again to ensure easy reference.

Could you please review the power stage and gate drive sections and let us know if you see any concerns or recommended improvements?

Looking forward to your feedback.

Best regards,
Thumula Bhargav

Hi Thumula,

Sorry for the delay. I was out of town on vacation.

Is it possible for you to share this as an attached PDF on the post? My company firewall does not allow me to directly access google drive.

Thanks!

Joseph

Hi Joseph,

No problem at all — I hope you had a great vacation!

Yes, I am sharing the schematic as an attached PDF in this post for your convenience. Please let me know if you’re able to access it without any issues.

Looking forward to your review and feedback on the schematic.

Thank you!

Best regards,
Thumula Bhargav

BLDC_DRIVER_POWER_BRD_V2 (1).pdf