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UC3638: Changing the reference voltage results in unexpected behaviour

Part Number: UC3638

I am using the UC3638 in the 20 pin SOIC package.

I'm using a single supply (+12V) driving an 'H' bridge as per the application note for the TEC controller.

The INV pin is driven via 100k from a DAC and 100k to COMP.

PVset is at 1V, RT at 2k7, CT at 750pF.

With Arefin left open (except for 100n decoupling cap), Aref is 5.95V and ramp on CT shows a 5V p-p 100 kHz signal centred on 6V. All Aout and Bout pins are showing waveforms as expected with DAC disconnected.

I want to centre the ramp and CSout on 2.5V to suit the ADC circuitry monitoring the currents. (the datasheet suggests 2V to 10V is possible)

I tried connecting 2.5V to Arefin. I get 2.8V on Aref, the ramp is 5V p-p centred on 4.5V and the Bout pins give no signal regardless of DAC input.

I then tried connecting Arefin to 0V (disables buffer according to datasheet) and connecting 2.5V to Aref. Now I get a 10V p-p ramp centred on 5V at 40 kHz! The CSout pin and INV pins are at 2.5V though.

Has anyone tried using a different reference voltage on this device?

Any help appreciated.

  • Hi David,

    We will investigate and reply soon.

    While waiting, would you try adjusting the PVset to .8V when AREFIN= 0V and AREF = 2.5V? You may be out of headroom.

    Also what is the DB voltage? As an experiment, can you try conneting DB to REF? This should result in zero deadtime.
  • Rick,

    Divider is 360/3k65/1k from REF to ground.
    I think this gives me 0.4V Deadband, and 1V PVset.
    Connecting DB to ref widens the drive pulses on the Aout pins slightly, but the Bout pins still don’t work.

    On another board, we disconnected the 2.5V to Arefin and the circuit works beautifully, but we now need to change our DAC/ADC/current monitor circuits to handle 6V as the centre point.
    We can work with that in the meantime but it’s extra circuitry.


    David Thomson
  • Hi David,

    On another board, we disconnected the 2.5V to Arefin and the circuit works beautifully, but we now need to change our DAC/ADC/current monitor circuits to handle 6V as the centre point.
    We can work with that in the meantime but it’s extra circuitry.

    What happens if you change PVset to 0.8V instead of 1V?
  • Rick,

    I changed PVset to 0.8V by putting as parallel resistor of 3k9 across the 1k on the PVset divider chain.

    The sawtooth reduces to 3.6V p-p, and the dc voltage (at no drive)  on both the CSout and Aref pins drops from 2.83 to 2.53 V. So far so good.

    I can now get 6V output drive in one direction by changing the drive into the INV/COMP pins. But nothing in the other direction.

    However, when I started off, I tried just holding the 3k9 resistor on by hand and found that when I removed it, the whole chip started working just fine and I could get 11V drive in both directions!

    Cycling the power returned it to the initial unipolar state, but the process could be repeated.

    It seems that selecting a 5V p-p sawtooth with a 2.5V reference causes some sort of internal latch-up.

    We have now decided to stick to using the 6V centre tapped Arefin and that works just fine.

  • Hi David,

    Thank you for running the experiment. There is a note on page 9 of the datasheet discussing the need for sufficient headroom for the triangle waveform. Trying to run the triangle waveform all the way to 0V would not be recommended.

    Please let us know if we can be of further assistance.