This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8350: DRV8320 - Gate Driver and possible Charge Pump Failure

Part Number: DRV8350
Other Parts Discussed in Thread: DRV832X, CSD18542KTT, CSD19532KTT, DRV8320

I have implemented a motor drive initially with a DRV8320S and migrated to a DRV8350S due to hardware failures. In testing the DRV8350 design I have had my first failure where a gate drive has a much lower impedance to ground as compared to the other two gate drives. The CPUV (charge pump under voltage) and a VGS fault bit get set whenever I try to use the driver. 

In the design with the DRV8320S we found the protection offered by the VDS_LVL to be insufficient for overcurrent protection given the large variance of Rdson over gate voltage and temperature. We were having failures where the fets would get shorted in all different manners, gate to drain, gate to source, source to drain and all three terminals shorted. Additionally the gate drivers in the DRV would fail shorted (or low impedance) to ground. To resolve the issue we added a safety circuit that monitors the total lowside current coming from all lowside FET sources and if tripped sets all INL signals low. This circuit also protects against the issue described in [1] where the chip starts up in 6x mode with unknown/wrong INL and INH values. We also migrated to the DRV8350S to increase our maximum voltage figuring the part would be more robust against voltage spikes. 

Given that we have just had another failure on the bench with the DRV8350S with the safety circuit and higher voltage part we are looking for potential causes. What could cause a gate drive in the DRV83xx chip to fail? We were testing the external overcurrent safety circuit when the driver failed. The drive is configured in 3x mode and there is a fixed 2/3 duty cycle on phase A and 1/3 duty cycle on B and C which allows the current to grow quickly. The overcurrent safety circuit properly tripped and the next reset of the DRV we found the gate driver broken for phase A. One possible fault could have been our IDRIVE settings as mentioned in [2]. I had just been increasing the values and set the to a value below where I could see ringing on the gates or phase A connection point. We did successfully run the test at lower IDRIVE settings without the part becoming damaged. Is there a way to determine save IDRIVE and TDRIVE settings? Should TDRIVE or IDRIVE be prioritized first when adjusting gate drive characteristics?



  • Hi Allen,

    We are looking into these points and will get back to you.
  • Hi Allen,

    Clarifications, if you can provide them:

    - For the DRV8320S, did you see the variances in the Rdson of the EVM FETs? I wonder if the variance you see relates to layout.
    - For DRV8350S: which IC are you specifically using? Also, are you utilizing the EVM?
    - The Idrive settings you are manipulating are when using DRV832x or DRV835x? I see you write that you cannot use DRV8350S without seeing the CPUV, VGLS faults. Is that always the case?
    - Determining safe IDRIVE value is about how fast you want to PWM the FETs and if that is enough time to charge the gate capacitance of the FET. Increasing the Idrive helps charge the FET. Have you looked at our IDRIVE, TDRIVE app note? Section 1.4.1 has an example on how to calculate IDRIVE and section 2.2.2 the guidelines to follow to determine the TDRIVE. I would first determine your Idrive to turn on the FET effectively and then manipulate Tdrive to wait long enough for the gate voltage to rise to the necessary value.
  • We are using the CSD19532KTT on the DRV8350RS design and on the CSD18542KTT DRV8320RS design. If I look at figure 8 of the CSD18542KTT there is a difference of .9-1.5x difference between 0 and 100c which the fets could experience between startup and running hard which corresponds to a similar range in trip current from nominal. Furthermore because the fets have such low on resistance the Vds level is small and there is little granularity in the setting for current levels ~20A. I don't think the variation is due to layout, this is just theoretical variance.

    We are using the DRV8350RSRGZT on a custom baseboard, the same board we were using the DRV8320RS modified slightly to use the higher voltage part. No EVM.

    Most recently I modified the IDRIVE value on the DRV835x and destroyed one DRV chip which resulted in persistent CPUV and VGLS fault on that DRV chip. The DRV832x had a variety of failures many of which resulted in broken DRV chips with VGS faults but I cannot be certain what lead to the failure. As soon as the DRV835x gate drive failure I wrote the original post. Larger values of IDRIVE result in bad ringing which I think may have happened.

    Reference [2] in the original post suggests that there are values of IDRIVE that can damage the DRV chip so while the application note gives recommended values it doesn't discuss limits. Using the CSD19532KTT (100V part) It seems like the smallest values of 10mA and 20mA source and sink respectively result in switching times of 560ns and 280ns respectively. These seem appropriate for our application.
  • Hi Allen,

    Thank you. Let me discuss with team as to how we should tackle recommended values for IDRIVE/TDRIVE, the ringing seen at higher values, and the lower impedance measurement you see on DRV835x. Is there any other points you would like clarifications on?

    Additionally, I was wondering what test setup you had to measure the impedance to ground and how you layed out the DRV8350 board ground pour. Do you have dedicated power/ground planes?

    In terms of your application, what are the questions you have in terms of DRV835x and DRV832x to get you in a operating state?
  • A point of clarification: the low impedance measurements were made from the gate to ground and they signified failed gate drives.

    The DRV8350 board is layed out with a power and ground plane, however the lowside sources all connect to a large pour on the top side so we can measure the total lowside current for our safety circuit. The large pour is connected to the ground plane though a power measurement resistor.

    At the moment we are operating however of the DRV832x boards we have a 20% fall out rate with a large portion having failed gate drives. Of the DRV835x I have had one failure so far (much less test time) which was a gate drive failure. We are trying to understand the reasons why the gate drive failures are occurring since we can't have a 20% failure rate. I would be happy to provide the design files if I can provide them privately.
  • Hi Allen,

    Please, accept friend request so I can access the design files privately.
  • Hi Allen,

    We are investigating these designs. Clarifications:

    1. Have you tried using a new DRV8350 board with only the IDRIVE settings 10mA and 20mA, source and sink respectively, you mentioned above?

    2. What are your VBUS and continuous/instantaneous current load?

    3. Two layout clarifications: Are you using almost identical board layout between the DRV8320 board and DRV8350 board? Is your power and ground plane only one plane or two separate planes?

    4. Are you utilizing the same motor/load for both DRV applications?

  • 1. Yes, I currently am running at 10mA and 20mA and haven't broken any drives yet on the DRV8350 board for fear of breaking more boards.

    2. Vbus is 48v and 10A continuous, 20A instantaneous, currently my load is only using 6.5 cont, 15 instantaneous.

    3. The board is almost identical between the DRV8320 and DRV8350, there is a common low side sense resistor in the DRV8350 board which requires a pour on the top side that is connected to the ground plane via the sense resistor. Both designs utilize two seperate planes for power and ground. Our stackup looks like:

    power - split plane, all VBUS over common plane, all logic level over a common plane except the logic signals to the DRV
    ground - plane

    4. Yes, we are using the same motor/load for both DRV applications.
  • Hi Allen,

    Thank you for the discussion. I will wait for further input on your end in the future, if the need is needed. Closing this thread now.
  • Hector,

    After additional testing we are getting DRV failures where the fault bit is set in the fault status register and the GDUV bit is set in the VGS Status 2 register. What could cause the GDUV bit get set effectively permanently?



  • Allen,

    Are you still using low iDrive settings?

    Can you share your layout and schematic? Sorry if this has been shared previously, I am taking over this case from Hector.


  • Allen,

    I am closing this thread due to inactivity. Please post again if needed.