Hello,
I was wondering if I could get some help with an issue I am seeing while using the DRV8704 in my application. I don’t intend to drive a motor but want to drive thermoelectric cooler (TEC) devices. At this point, I am driving resistive loads for test purposes to validate my hardware design.
I have two DRV8704 devices on my board, driving a total of four full bridges. Initially, I was driving one bridge at a time to prove each individual channel worked as expected. I was able to run single channels individually at up to 7A (in either direction, with respect to the 50% midpoint). I started to see issues when driving two bridges from the same DRV8704 device. The channel that was driving the lower current of the two bridges would hit a point where it went into either over-current protect mode or sometimes reported a pre-driver fault. It seemed to always be the channel pushing the lower current of the two, when a cumulative load between the two channels hit around 5A in the same direction. I was able to run one channel at 5A in a positive direction, and the other in the other direction, suggesting that the issue only arises when driving a certain magnitude of current in the same direction, with influence from the channel driving the heavier load imposing onto the other channel, causing either a genuine or artificial fault (as the two bridges are not synchronised and will be operating at marginally different frequencies due to component tolerance). My first thought was that noise was being induced onto the secondary channel’s sense resistor and the device would hit it’s chopping current limit, which in turn would upset the bridge by going into slow decay mode and then triggering a genuine over-current fault. I tried increasing the blanking time and setting the ISGAIN register to minimum, but the issue remained.
My design has a VM of +48V, and a dedicated PWM chip provides the PWM signals to the driver, where I can program the ratio / duty-cycle for a desired current across my resistive loads. The outputs from the bridge were low pass LC filtered (see this post for the original design, however component values have changed significantly since then, but the general setup is the same: e2e.ti.com/.../754284. I followed the basic layout from the datasheet (figure 22 in SLVSD27-OCTOBER 2015), rather than the layout of the EVM board due to PCB space, however it is interesting that they differ. My PCB is 6-layer, with all parts placed on the topside, with layer 2 being a solid ground plane, and the gate switching signals routed on layer 3.
I am seeing this problem: without a load attached, the gate drive signals look clean. Once a load is attached, I get ringing on the gate drive signals when the duty-cycle changes and hence current through the resistive load increases. The noise is on the high and low-side FET gate drives, on the FETs where the high-side pulse width is decreasing and the low-side increasing (indicating the current magnitude / direction). The noise spike is worse on the high-side gate and seems to coincide with the switching points of the other high and low-side FETs in the same bridge. I have taken measurements carefully with a differential probe and am confident that the voltage spikes are present. There is substantial jitter on the low-side gate drives also.
High-side gate drive:
Captures at different times showing there are two spikes coinciding with the turn-on of the opposite pair of high-side and low-side FETs in the same bridge:
Low-side gate drive (disturbance can be seen on rising edge in addition to falling edge jitter):
I tried lowering the supply (VM) voltage to +28V and while the noise spikes did reduce *very* slightly, they seem to start at around 0.5A and then plateau at approximately +2V with continually increasing current, indicating that it is most likely a pure di/dt switching problem. I tried removing all capacitors on the LC output filters as well as the ceramics between the two filtered legs, but the results are the same. The series inductors are still present however. I also tried lowering the IDRIVE settings which helped slightly but then reduced the rise and fall times of the FETs to unacceptable limits. I am not sure if this all simply points to a PCB layout issue, but I did try and stick to the datasheet. Unfortunately, I can’t post images of my layout for confidentially reasons. I have not seen any evidence of cross-conduction, but this ~+2V spike is just shy of the minimum VGS threshold of the MOSFETS.
I plan to next try and filter out any switching spikes detected by the sense resistor to see if the device was artificially sensing it’s chopping current limit, but this will just be masking the root issue.
Thank you in advance for any advice.
Regards,
Stephen
