DRV2605L-Q1: DRV2605l-Q1 Layout

Fabio Soriano

Intellectual 2345 points

Part Number: DRV2605L-Q1
Other Parts Discussed in Thread: DRV2605L

Hi Team,

I need some info on the layout of DRV2605L-Q1 for an AA.

On datasheet Page 58 there is some reference on WCSP and not VSSOP that is the automotive version.

Is the section 10.1.1 - Trace Width - still correct for VSSOP package?

In case it is correct can you explain why with a width of the single PAD of "270um" it is advised to have a track width of maximum 100um?

During the product industrialization phase, their PCB supplier is able to guarantee this 100um track width but with a low tickeness of 17um ... can it be fine?

Which limits must we respect ?

Please, let me know!

Regards,

Fabio

over 4 years ago

0 Luis Fernando Rodriguez S. over 4 years ago

TI__Guru* 84915 points

Hi, Fabio,

I will search for more information about this and will answer in few hours.

Best regards,
Luis Fernando Rodríguez S.

0 Luis Fernando Rodriguez S. over 4 years ago in reply to Luis Fernando Rodriguez S.

TI__Guru* 84915 points

Hi, Fabio,

It seems that the information in the datasheet doesn't apply for the VSSOP package. Only section 10.2 can be used as a layout recommendation for the DRV2605-Q1 (VSSOP). We will work to modify this in order to prevent confusion.

In order to design a correct layout, the example board layout dimensions should be respected as mentioned in the following document:

http://www.ti.com/lit/ml/mpds035c/mpds035c.pdf

Please let me know if you have additional questions or comments.

Best regards,
Luis Fernando Rodríguez S.

0 Fabio Soriano over 4 years ago in reply to Luis Fernando Rodriguez S.

TI__Intellectual 2345 points

Hi Luis,

Can you confirm that the minimum width to be respected must actually be between 75um-100um?

I need also an explanation about its real benefit.

Regards,

Fabio

0 Luis Fernando Rodriguez S. over 4 years ago in reply to Fabio Soriano

TI__Guru* 84915 points

Hi, Fabio,

I would recommend to use a trace with a similar width of the DRV2605L-Q1 pads. This width is normally used in our EVMs and it works correctly:

http://www.ti.com/lit/ug/slou348b/slou348b.pdf#page=25

However, the minimum width is 75um - 100um in order to ensure that the traces will support the current of the DRV2605L pins. It also allows for plenty of clearance between adjacent pads while routing away from the chip.

Best regards,
Luis Fernando Rodríguez S.

Motor drivers

Motor drivers forum

DRV2605L-Q1: DRV2605l-Q1 Layout