Other Parts Discussed in Thread: DRV8701
Hello,
I have a basic question about the DRV8704.
I read the technical document SLVA966A.
The DRV8704 does not list in the Table 1.
Is the DRV8704 the "Smart Gate Driver"?
Best Regards,
Naoki Aoyama
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Hi Aoyama-san,
Yes the DRV8704 is a Smart Gate Driver.
Hi Rick-san,
Thank you for your reply.
I do not understand the operation of the Smart Gate Drive well.
I attach the file include the recognition of mine.
Could you check the file?
Best Regards,
Naoki Aoyama
Hi Aoyama-san,
Question 1: If the gate voltage reach a high level before the end of the tDRIVE , the gate drive current change to a weak current.
Is my recognition correct?
The Gate drive remains set to the same level during the tDRIVE time. As the FET gate charges, less current is provided to the gate of the FET.
Question 2: It is mentioned “During high-side turn-on, the low-side gate is pilled low” on the DS.
Is this waveform correct?
How much the value of the pulling current? Is it set by IDRIVEN?
Yes, the waveform is correct. The sink current is ~60mA typical.
Hi Rick-san,
Thank you for your reply.
I understood the operation of the DRV8704.
It seems the gate drive method of the DRV8704 and the gate drive method
of the DRV8701, DRV8702 and DRV8703 are difference.
Is the DRV8704 more susceptible to a noise generated by dV/dt than the DRV8701, DRV8702 and DRV8703?
Best Regards,
Naoki Aoyama
Hi Aoyama-san,
The gate drive method is different.
The DRV8704 may be more susceptible if the routing is sub-optimal.