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DRV10866: Jitter spec on Fg signal

Part Number: DRV10866


I'm using the DRV10866 motor control chip to run a small BLDC motor at about 3600 rpm. In my application once-around jitter is critical. I'm using the Fg signal as feedback in an FPGA control loop. 

1. Is the Fg signal generated by an analog zero-crossing circuit or does the timing also depend on any embedded controller clock on the DRV10866 ?

2. What is the inherent jitter spec on Fg due to the DRV10866 bemf detection? If no spec is set then what is a typical value?

3. Does it matter whether a motor control loop uses the rising edge or falling edge of Fg?

4. How is the 50% duty cycle of the Fg signal generated?