Hello Team,
I'm Yuta Kurimoto from TIJ.
Now our customer has been evaluation DRV3245AQ-Q1. They have a question about the trigger which activates the VDS/VGS monitor.
Datasheet says "The tBLANK time is inserted after each switch-on transition (LOW to HIGH) of the output gate drivers is commanded.", but they don't know how to interpret this.
Q. What is the trigger to activate the VDS/VGS monitor?
For example, they are guessing the trigger is
- DRV3245-Q1 monitors the INH/INL PWM signal by internal comparator. When the INH/INL turns to HIGH, it will trigger to activate the VDS/VGS monitor.
- DRV3245-Q1 monitors the state of internal push-pull stage by comparator. When the high side FET of the push-pull turned ON, it will trigger to activate the VDS/VGS monitor.
- DRV3245-Q1 monitor the Gate voltage(w.r.t the Source) for external FET. When the gate voltage exceed some threshold, it will trigger to activate the VDS/VGS monitor.
Thanks,
Yuta Kurimoto