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DRV8704: Output signals form?

Part Number: DRV8704
Other Parts Discussed in Thread: DRV8703-Q1

Hi,

I m planning to use DRV8704 for one of my projects. I m curious to know how DRV handles PWM input. Will it produce complementary signal on the output for a specific half bridge to handle or is it mirored pwm signal for one high side FET and one low side FET?. If i send one edge aligned PWM signal on AIN1 with 30% duty cycle what will be the output on A1HS, A1LS, A2HS and A2LS?

  • Hi Nemanja,

    See the following section snipper of the datasheet for more information:

  • To expand:

    1. If xIN1 = 1, then xOUT1 = 1, which means the high side FET's gate of xOUT1, x1HS, is = 1. x1LS = 0.
    2. If xIN1 = 0, then xOUT1 = 0, which means the lowside FET's gate of xOUT1, x1LS, is = 1. x1HS = 0.

  • Hi Hector,

    Thanks for the info. I read the documentation couple of times, tested DRV8704, tried with center and edge aligned mode and i have next result. I will follow your analogy.

    1.if xIN1 = 1, then xOUT1 = 1, which means the high side FET's gate of xOUT1, x1HS, is = 1. x1LS = 0 but also x2LS=1.

    2.if xIN1 = 0, then xOUT1 = 0, which means the lowside FET's gate of xOUT1, x1LS, is = 0. x1HS = 0.  There s no complement whe pwm is 0.

    Seems to me that complementary output doesnt apply when low pwm input is supplied. My question now is can this driver control one half bridge hypothetically if we ignore xOUT pins and all dependency pins? Would 40% od duty cycle in edge aligned mode on one input channel for example AIN1 produce 40% of period HIGH output to A1HS and the same percentage of LOW to A1LS and rest 60% of period LOW to A1HS and HIGH to A1LS?

    I m pretty sure about connection and also with configuration for the parameters. 

    Thanks

  • Hi Nemanja,

    Thank you for the correction. Yes, you are correct, but it must be expanded some more. Since you are trying to drive a half-bridge, you need to look at the PWM table based upon how you need the xOUT1 to behave (1, 0 or High Z) and set xIN1 AND xIN2 to get the xOUT1 output you need. Say your load is connected to xOUT1. The PWM table content that matters to you will be as follows.

    I am not clear as to how you are trying to drive. Can you clarify more the following statement? Thank you.

    Would 40% od duty cycle in edge aligned mode on one input channel for example AIN1 produce 40% of period HIGH output to A1HS and the same percentage of LOW to A1LS and rest 60% of period LOW to A1HS and HIGH to A1LS?

  • Hi Hector,

    I appreciate your involvement. This was an example but it doesn't matter since you clarified me some things. I m trying to drive brushed maxon dcx 32 in unipolar way and i have certain issues. By doing it bipolar drive I can see normal current waveform flowing in right directions, but it has slightly bigger peak amplitude. Unipolar driving requires 4 diferent states of full bridge forward, reverse, brake low side, and brake high side. From the documentation i cannot see how to enable brake on high side (how to enable only high side fets). There's HI-z mode in which current goes in stabilized near zero mode during unipolar driving. I could perheaps jump this with some filter, it will provide certain latency to OCPH but thats another question. So, can I use full uniploar driving? Can i enable high side fets only?

    Best

  • HI Nemanja,

    I see. I do not see how the DRV8704-Q1 can do high-side braking. Now, with DRV8703-Q1, you can do high-side braking in Independent PWM mode. If you are driving two motors, you can use two DRV8703-Q1s.