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Original question:

DRV8873: DRV8873HPWPRQ1

DRV8873: DRV8873HPWPRQ1

Subramaniam NS
Prodigy 195 points
Part Number: DRV8873


Dear Rick,

Please note the HDB sections are being tested on the board.
HBD device is DRV8873-Q1. The hardware implementation was sent for your review during the design phase.

While testing I observe that fault status does not reflect open load fault status when load is disconnected.

Testing condition.
IN1 and IN2 is OFF that is 0V.
nOL pin is driven low.

When load is connected to OUT1 and OUT2 status is high.
When load is disconnected from OUT1 and OUT2 status remains high in powered on condition, even nSLEEP is given a low pulse of of 11uS to clear the previous status.

Thanks and Regards,

Subramaniam

  • 0
    Prodigy 195 points

    Hi,

    Please clarify about NODE mentioned in the table 7 and 12 in the device datasheet.

    We observed with 12uSec pulse on nSLEEP did not reflect the updated open load condition. For the same we had to extend the pulse to 40 usec.

    We require the updated nFAULT status without sending the device to sleep mode. Please let us know the possibility.

    As the datasheet waveform confirms clearing the fault status registers with nSLEEP given upto 20usec reset pulse, the same is not happening on as mentioned in datasheet rather the nFAULT line always stays HIGH post nSLEEP pulse deasserted.

    We checked the OLP did not happen just before the IN commands were given, the status remained HIGH even in this case.

    Even during OLA, the 12usec nSLEEP reset did not reflect the correct status of open load.

    Thanks and Regards,
    Subramaniam

  • 0 in reply to Subramaniam NS
    TI__Guru 56650 points

    Subramaniam,

    "HBD device is DRV8873-Q1. The hardware implementation was sent for your review during the design phase."

    Rick will come back after thanksgiving, next Monday.

    Happy thanksgiving.

  • 0 in reply to Wang5577
    TI__Guru** 114905 points

    Hi Subramaniam,

    Sorry for the delay.

    Table 7 describes the available functionality if the motor is not connected between OUT1 and OUT2. NODE1 is one side of the load, and NODE2 is the other side of the load. See Figure 11 as an example. NODE 1 is connected to OUT1 and NODE 2 is connected to GND.

    Table 12 describes that typical upper limit of motor resistance that may fail the OLP check. 

    We have not seen this behavior previously.

    Can you provide a little more information?

    How are you PWM'ing the inputs when MODE is set to high?

    What is the PWM frequency, and on time?

    Also do you  have any additional components connected to the outputs (inductors/chokes/ferrite beads/capacitors)? If so, please provide a snippet of the latest schematic in case there have been changes.

  • 0 in reply to Rick Duncan
    TI__Guru** 114905 points

    Hi Subramaniam,

    For now, we will mark this thread as TI Thinks Resolved since we are communicating privately.

    If we find something that can help the community, we may share the results.

  • 0 in reply to Rick Duncan
    Prodigy 195 points

    Dear Rick,

    I have posted the query to private message as directed. Please respond to the same.

    Thanks and Regards,

    Subramaniam