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DRV8343-Q1: Gate Drive Value

Brett Nourrcier
Intellectual 905 points
Part Number: DRV8343-Q1
Other Parts Discussed in Thread: DRV8301

Hey TI - I am driving a DRV8343S-Q1 with a F280049C MCU.  I have the DRV in 6x PWM mode and have verified SPI communications. All seems well.

But - after I enable the drive and set its SPI registers - I measured the voltage at the motor connections to ground and saw ~ PVDD voltage.  When I measured the voltage from each high side gate to ground I saw the same voltage.  I set the 6 PWM outputs to GPIO on the MCU and set all to 0 to confirm something strange wasn't going on the MCU side: saw the same (high on motor connection, high gate voltage on high side MOSFETS).  When I set the 3 low side PWM signals to 1, the motor connections measured 0 volts to ground and the high side gates measured 0 to ground. 

I confirmed that placing the PWM outputs in HiZ did not correct the issue. I also looked at the sensorless code for the DRV8343 EVM and verified they set all PWM outputs to 0 when they disabled the drive...

Bottom line: I was expecting both gate outputs to read 0 when both PWM inputs were 0 (Table 1 in DRV datasheet).   I can work around the issue but want to make sure this is not an issue on my side. Can you please comment?

Thanks!

Brett

  • 0
    TI__Guru 61380 points

    Brett,

    Thanks for posting on the MD forum!

    The High Side gates will only be ON if the voltage from their Gate to Source is more than a few volts. This means that you should subtract the Source voltage from the gate voltage when checking if the high side gate is ON.

    The phenomenon you are seeing is caused by a very small leakage path inside the device that can cause PVDD voltage to be seen at the gate and source of the high side FET. This leakage is less than 1mA and is normal for the floating gate design this device uses where the gate pulldown is referenced to the source. The source of the high side FET is internally shorted to the gate to ensure that the high side gate stays OFF.

    Regards,

    -Adam

  • 0 in reply to Adam Sidelsky
    Intellectual 905 points

    Thanks Adam.  And you are correct - the gate to source voltage is ~ 0.  I was concerned because I did not see the same when i looked at a DRV8301 inverter and I worry about connecting and disconnecting my motor while voltage is on the motor leads.  I am thinking I should disable the ePWMs so the High Side gates are driven low and the Low Side gates are driven high (vice having them go HiZ).  This would kill the voltage on the motor leads...TI seems to default to HiZ in their reference designs.  Do you see any issues driving the high side gates low and the low side gates high when the ePWM is disabled?

    Thanks again for all of your help!

    Brett

  • 0 in reply to Brett Nourrcier
    TI__Guru 61380 points

    Brett,

    Sorry for the delay.

    The reason for this difference is that the DRV8301 uses a different architecture and the leakage paths are different.

    No issue with your plan above!

    Regards,

    -Adam