I am currently designing the DRV8889-Q1 in out application.
I don't understand the topology of the below blockdiagram.
Below picture, I think that the capacitor between the CPH and CPL acts as boosting up to control the high side gate driver like VCP.
So, without the VCP pin, the CPH pin can control the high side gate driver and don't need the vcp pin.
please explain the topology the below blockdiagram.
thank you so much