I'm using a DRV8844 to drive a solenoid rated below 500mA and am running into some issues with the bulk capacitance.
The supply for VM comes from a circuit that dynamically switches between two voltages: a high voltage to turn the solenoid on quickly, and a holding voltage to keep the solenoid open (for theory of operation, see: Electronic Design: What's All This Solenoid Driver Stuff Anyhow?
Our specific application has two independent power rails, called Vin and Vhold. Vin is a high (~48V) voltage meant to turn the solenoid on quickly, and Vhold is the holding voltage of the solenoid (~24V). Each power rail comes into the board from a dedicated supply. Each rail goes to a high side switching circuit, which are both controlled by a microcontroller via a high side driver circuit, and the circuit ensures that only one rail is active at a time (though there is also a schottky meant to OR the voltages and prevent backfeeding a supply). The output of each high-side circuit goes to VM of the DRV8844, and a bulk capacitor between VM and Vneg on the DRV8844. We used 100uF for the bulk capacitance initially, but the relatively high resistance of our solenoid means that when the voltage transitions from Vin to Vhold, the bulk capacitor doesn't discharge quickly enough and the transition between Vin and Vhold is longer than we would like. Based on some back-of-the-envelope calculations and some initial testing, we believe we need a bulk capacitor around 3.3uF for the driver to transition quickly enough between Vin and Vhold for these solenoids.
The datasheet for the DRV8844, as well as a previous E2E question (https://e2e.ti.com/support/motor-drivers/f/38/t/555963) indicated that the minimum recommended bulk capacitance is 10uF. Naturally, we're almost an order of magnitude out of this recommended spec with this 3.3uF capacitor. That said, if we are confident in the ability of our external supplies to deliver sufficient current without voltage droop at the VM input, is there any fundamental/architectural reason why we couldn't lower the bulk capacitance at VM to around 3.3uF? Our initial testing looks like it performs just fine, as we would expect, but given that these are anticipated to go through a large number of cycles for an extended period of time, I thought it important to ask whether derating the capacitance specification is going to result in deleterious effects further down the line or whether it's just unknown territory from TI's perspective.
Any input is much appreciated.
