DRV8876: Question about Cycle-by-cycle current chopping

Hi  Fujihara-san,

Thank you for posting to the motor driver's forum.

1. The cycle-by-cycle current regulation frequency will closely match the control input (IN1, IN2) PWM frequency. So the 0Hz to 100kHz PWM frequency range will be also valid for the current chopping frequency.

The duty cycle will vary depending on the time it takes for IOUT to exceeds  I_TRIP. Below is a diagram of the cycle-by-cycle current regulation waveform. As you can see, in some cases, the duty cycle of VOUT is larger when the time for IOUT to reach ITRIP is longer.

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• The minimum decay time will be approximately equal to t_rise+t_fall+t_dead= 600ns.
• The difference between "Chop" and "decay" comes down to whether the device is in current regulation mode or not. If I_OUT is below I_TRIP at the end of the drive time (T_ON of control input), the H-bridge will go into "decay" for T_OFF. The decay mode can be set to either Coast (all FETs High-Z) or Brake (both low-side FETs enabled). On the other hand, if I_OUT is above I_TRIP by the of the drive time, the device will go into "Chop" current regulation decay (both low-side FETs ON) until the next control signal edge rise. 

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