Hi Team,
I have some questions about DRV8803's specification and design requirements. Could you give me some comments to close my customer's questions below?
[Design requirements]
1. Could you tell me TI recommendation of VM bypass cap value? 0.01uF x 1 is enough?
2. Which of the following pins should be connected to AGND or PGND?
5pin :
12pin :
PAD :
3. Is it OK to leave RESET pin open if it would be not used?
[Specification]
1. Could you tell me Absolute Maximum Ratings of nENABLE, IN and RESET? Can we regards it as –0.5~7V?
2. Could you tell me recommended PWM frequency range of DRV8803?
3. Could you tell me the difference between following conditions?
RESET:H nENABLE:L
RESET:L nENABLE:H
Regards,
Takashi Onawa