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DRV8803: specification and design requirements

Part Number: DRV8803

Hi Team,

I have some questions about DRV8803's specification and design requirements. Could you give me some comments to close my customer's questions below?

[Design requirements]

1. Could you tell me TI recommendation of VM bypass cap value? 0.01uF x 1 is enough? 

2. Which of the following pins should be connected to AGND or PGND?
      5pin : 
      12pin : 
      PAD : 

3. Is it OK to leave RESET pin open if it would be not used?

[Specification]

1. Could you tell me Absolute Maximum Ratings of nENABLE, IN and RESET? Can we regards it as –0.5~7V?

2. Could you tell me recommended PWM frequency range of DRV8803?

3. Could you tell me the difference between following conditions?
      RESET:H nENABLE:L
      RESET:L nENABLE:H

Regards,

Takashi Onawa

  • Hi Team,

    Sorry, I got one additional question.

    4. Do you have Vf voltage variation data(due to process variation)? If you have, please share it.

    Regards,

    Takashi Onawa 

  • Onawa-san,

    Please give me some time to investigate the answers to you questions.

  • Onawa-san,

    1. Could you tell me TI recommendation of VM bypass cap value? 0.01uF x 1 is enough? 

    Per the Typical Application section, 8.2, we recommend a 0.1uF low ESR ceramic bypass cap on VM and a bulk capacitor that is sized according to the output load. A general rule is 2-3uF per watt of output power.  For example, if combined output load is 10W, use a 30uF bulk.

    2. Which of the following pins should be connected to AGND or PGND?
          5pin : 
          12pin : 
          PAD : 

    Please see Figure 13 in the datasheet.  All these pins should be connected together at the PowerPad and connected to a single point ground, PGND.

    3. Is it OK to leave RESET pin open if it would be not used?

    Yes, there is an internal pulldown resistor on this pin.

    [Specification]

    1. Could you tell me Absolute Maximum Ratings of nENABLE, IN and RESET? Can we regards it as –0.5~7V?

    These are considered digital input pins, so -0.5V ~ 7V is correct.

    2. Could you tell me recommended PWM frequency range of DRV8803?

    This is listed in section 7.1 of the datasheet.  0 Hz to 100 kHz is the suggested range.

    3. Could you tell me the difference between following conditions?
          RESET:H nENABLE:L
          RESET:L nENABLE:H

    Please see section 7.4.2 of the datasheet.  For the first case, the internal logic will be RESET, all faults cleared.  The outputs will be ENABLED, but since RESET is held HIGH, the inputs will be ignored so the device outputs will not follow the inputs.  

    For the second case, the device will be out of reset, but the outputs will be in HIZ state.  

    Unfortunately, I do not have the Vf variation data for the device.