Can you please help interpret High voltage tolerant logic input (Wake) table on page 7 of the datasheet?
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
The Wake pin's absolute maximum is 45V. The intent to allow the Wake pin to be used by a digital logical rail or a voltage closer to VM, as these threshold sits right around the low typical logic rail of 1.8V.
As such, logic low and logic high can be interpreted as the point where the previous logical state will be flipped. If the Wake signal is held to GND or 0V, the signal needs to be greater than the Output logic high, voltage spec. So any voltage above 1.42V-1.75V will trigger the logical value to be flipped from "0" to "1" in digital logic. As such, a 1.8V rail would be able to clear the spec to send the signal to wake the DRV.
Inversely if the Wake signal's rail is held at a VM voltage, say 12V, then the voltage will flip from "1" to "0" once the voltage on the wake pin is less than the Output logic low voltage. This means, any voltage below 1.1V-1.41V will be interpreted as "low" to the digital logic of the DRV.
This spec's intent is to help with timing when Wake logic will be executed as different rails with different slew rates result in different timing before the Wake signal is actually flipped.