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DRV8860: The fault register read timing is inconsistent with the datasheet

Part Number: DRV8860

Hi Team,

The customer is experiencing below issue and needs your help.

The customer has questions about the beginning of the sequence of reading the fault register. If he writes the program according to the manual sequence, he will lose the highest bit when reading the data. If it is configured as follows, it can be read correctly.

Question 1: If he does not add CLK high and CLK low, the highest bit will also be lost.

Question 2: CLK_H();//? According to the datasheet timing diagram, it should be after LATCH_H; it cannot be read correctly after replacement.

uint16 DRV8860_ReadFault()

{

uint16 dat=0;

uint8 i;

CLK_H();//?According to the datasheet sequence diagram, no need

CLK_L();//?According to the datasheet sequence diagram, no need

CLK_H();

LATCH_H();

CLK_L();

LATCH_L();

CLK_H();//?According to the datasheet sequence diagram, it should be after LATCH_H;

LATCH_H(); 

//LATCH_H();//The following is consistent with the datasheet, missing MSB

// CLK_L();

// LATCH_L();

// LATCH_H();

/ // CLK_H();

for (i = 0; i < 8; i++)
{
CLK_H();
CLK_L();
dat <<= 1;
if (DOUT_PIN) dat |= 1;
}

for (i = 0; i < 8; i++)
{
CLK_H();
CLK_L();
dat <<= 1;
if (DOUT_PIN) dat |= 1;
}

LATCH_L();//
return dat;

Best regards,

Annie